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www.national.com pc87366 128-pin lpc superi/o with system hardware monitoring and midi and game ports general description the pc87366, a member of national semiconductors 128-pin lpc superi/o family, combines nationals system hardware monitoring capability with a musical instrument digital interface (midi) port and game port inputs for up to two joysticks. the pc87366 is pc99 and acpi compliant and offers a single-chip solution to the most commonly used pc i/o peripherals. system hardware monitoring provides minimum power con- sumption and maximum operating efficiency within the system environment. it integrates nationals diode-based or thermistor- based temperature sensor (tms) with nationals voltage lev- el monitor (vlm) for full pc system thermal control. the pc87366 monitors system voltages using 8-bit analog to dig- ital (a/d) conversion with seven analog input channels and four internal measuring points. the pc87366 also incorporates: fan speed control and monitor (fscm) for three fans, extended wake-up support for a wide range of wake-up events, system design protection features, a floppy disk controller (fdc), a keyboard and mouse controller (kbc), access.bus ? interface (acb), system wake-up control (swc), general-purpose in- put/output (gpio) support for 40 ports, an enhanced watchdog timer (wdt), a full ieee 1284 parallel port and two enhanced serial ports (uarts), one with infrared (ir) support. outstanding features l system hardware monitoring including: diode-based or thermistor-based temperature sen- sor (tms) voltage level monitor (vlm) with vid inputs l midi interface compatible with mpu-401 uart mode l game port inputs for up to two joysticks l extended wake-up support, including legacy/acpi power button support, direct power supply control in response to wake-up events, power-fail recovery l protection features, including chassis intrusion detection, gpio lock and pin configuration lock l fan speed control and monitor for three fans l serial irq support (15 options) l bus interface, based on intels lpc interface speci?- cation revision 1.0, september 29th, 1997 l access.bus interface, smbus ? physical layer compati- ble l 40 gpio ports (29 standard, including 15 with assert irq/ smi/ pwureqs interrupts; 11 v sb powered) l blinking leds l 128-pin pqfp package block diagram system wake-up serial port 2 ieee 1284 parallel port ports keyboard & mouse i/f scl access.bus floppy disk controller floppy drive interface keyboard & serial infrared interface interface control bus interface lpc interface i/o 3 control watchdog timer wdo serial port 1 serial interface outputs fan speed control & monitor interface mouse controller with ir gpio ports 3 monitor inputs sda serial irq analog inputs system parallel port interface diode interfac e smi ports hardware monitoring v ref midi interface midi & game ports game inputs wake-up events pwureq power control v dd v bdat v sb av dd national semiconductor is a registered trademark of national semiconductor corporation. all other brand or product names are trademarks or registered trademarks of their respective holders. ? 2000 national semiconductor corporation revision 2.01 november 23, 2000 pc87366 128-pin lpc superi/o with system hardware monitoring and midi and game ports
2 www.national.com features ? voltage level monitor (vlm) seven analog inputs that can support both positive and negative voltages four internal measuring points three thermistor-based temperature monitoring channels internal or external v ref vid inputs meets acpi and dmi requirements for system volt- age monitoring ? temperature sensor (tms) up to two remote diode inputs environment temperature sensing via an internal di- ode a/d analog channels provide thermal inputs to di- rectly sense die temperature of remote diodes meets acpi and dmi requirements for thermal man- agement standby mode to minimize power consumption ? extended wake-up legacy and acpi power button support direct power supply control in response to wake-up events power-fail recovery ? musical instrument digital interface (midi) port compatible with mpu-401 uart mode 16-byte receive and transmit fifos loopback mode support l game port full digital implementation supports up to two analog joysticks ? protection chassis intrusion detection (chasi, chaso) gpio lock pin con?guration lock ? 40 general-purpose i/o (gpio) ports 29 standard, with assert irq/ smi/ pwureq for 1 5 ports 11 v sb powered programmable drive type for each output pin (open- drain, push-pull or output disable) programmable option for internal pull-up resistor on each input pin output lock option input debounce mechanism ? fan speed control and fan speed monitor (fscm) supports different fan types speed monitoring for three fans o digital ?ltering of the tachometer input signal o alarm for fan slower than programmable thresh- old speed o alarm for fan stop three speed control lines with pulse width modula- tion (pwm) o output signal in the range of 6 hz to 93.75 khz o duty cycle resolution of 1/256 ? lpc system interface synchronous cycles, up to 33 mhz bus clock 8-bit i/o cycles up to four dma channels 8-bit dma cycles basic read, write and dma bus cycles are 13 clock cycles long ? pc99 and acpi compliant pnp con?guration register structure flexible resource allocation for all logical devices o relocatable base address o 15 irq routing options o four optional 8-bit dma channels (where applica- ble) ? floppy disk controller (fdc) programmable write protect fm and mfm mode support enhanced mode command for three-mode floppy disk drive (fdd) support perpendicular recording drive support for 2.88 mb burst and non-burst modes full support for ibm tape drive register (tdr) im- plementation of at and ps/2 drive types 16-byte fifo software compatible with the pc8477, which con- tains a superset of the fdc functions in the microdp8473, the nec micropd765a and the n82077 high-performance, digital separator standard 5.25 and 3.5 fdd support ? parallel port software or hardware control enhanced parallel port (epp) compatible with new version epp 1.9 and ieee 1284 compliant epp support for version epp 1.7 of the xircom spec- i?cation epp support a s mode 4 o f the extended capabilities port (ecp) ieee 1284-compliant ecp, including level 2 selection of internal pull-up or pull-down resistor for paper end (pe) pin pci bus utilization reduction by supporting a de- mand dma mode mechanism and a dma fairness mechanism
3 features (continued) www.national.com protection circuit that prevents damage to the paral- lel port when a p rinter connected to it powers up or is operated at high voltages, even i f the device is in power-down output buffers that can sink and source 14 ma ? serial port 1 (uart1) software compatible with the 16550a and the 16450 shadow register support for write-only bit monitoring uart data rates up to 1.5 mbaud ? serial port 2 with infrared (uart2) software compatible with the 16550a and the 16450 shadow register support for write-only bit monitoring uart data rates up to 1.5 mbaud hp-sir ask-ir option of sharp-ir dask-ir option of sharp-ir consumer remote control supports rc-5, rc-6, nec, rca and recs 80 non-standard dma support - one or two channels pnp dongle support ? keyboard and mouse controller (kbc) 8-bit microcontroller software compatible with the 8042ah and pc87911 microcontrollers 2 kb custom-designed program rom 256 bytes ram for data five programmable dedicated open-drain i/o lines asynchronous access to two data registers and one status register during normal operation support for both interrupt and polling 93 instructions 8-bit timer/counter support for binary and bcd arithmetic operation at 8 mhz,12 mhz or 16 mhz (programma- ble option) can be customized by using the pc87323, which in- cludes a ram-based kbc as a d evelopment plat- form for kbc code ? access.bus interface (acb) serial interface compatible with smbus physical layer compatible with philips i 2 c ? acb master and slave supports polling and interrupt controlled operation optional internal pull-up on sda and scl pins ? watchdog timer (wdt) times out the system based on user-programmable time-out period system power-down capability for power saving user-de?ned trigger events to restart watchdog optional routing of watchdog output on irq and/or smi lines ? system wake-up control (swc) power-up request upon detection of keyboard, mouse, ri1, ri2, ring activity and general-pur- pose input events, as follows: o preprogrammed keyboard or mouse sequence o external modem ring on serial port o ring pulse or pulse train on the ring input signal o preprogrammed ceir address in a preselected standard (nec, rca or rc-5) o general-purpose input events o irqs of internal logical devices optional routing of power-up request on irq, smi and/or pwbt out battery-backed event con?guration programmable v sb -powered output for blinking leds (led1, led2) control ? clock sources 48 mhz clock input lpc clock, up to 33 mhz on-chip low-frequency clock generator for wake-up ? power supplies 3.3v supply operation main (v dd and av dd ) standby (v sb ) battery backup (v bat ) all pins are 5v tolerant and back-drive protected, ex- cept lpc bus pins ? strap configuration base address (baddr) strap to determine the base address of the index-data register pair test strap to force the device into test mode (re- served for national semiconductor use) power supply and led con?guration (psldc0,1) straps to determine the power supply control func- tions and the v sb power-up defaults of led2 power supply on polarity (psonpol) strap to set pson active state and output type
4 www.national.com datasheet revision record revision date status comments november 1998 draft 0.3 speci?cation subject to change without notice; midi and game port information is incomplete january 1999 preliminary 1.0 speci?cation subject to change without notice; power supply control and led sections in chapter 2 are incomplete july 2000 2.0 datasheet with b2 errata included november 2000 2.01 tms/vlm characteristics updated
5 www.national.com table of contents datasheet revision record ............................................................................................................ 4 1.0 signal/pin connection and description 1.1 connection diagram ......................................................................................................... 15 1.2 buffer types and signal/pin directory .................................................................... 16 1.3 pin multiplexing ................................................................................................................. 21 1.4 detailed signal/pin descriptions ................................................................................ 23 1.4.1 access.bus interface (acb) .................................................................................... 23 1.4.2 bus interface ............................................................................................................... 23 1.4.3 clock ............................................................................................................................ 23 1.4.4 fan speed control and monitor (fscm) ..................................................................... 23 1.4.5 floppy disk controller (fdc) ...................................................................................... 23 1.4.6 game port ................................................................................................................. .25 1.4.7 general-purpose input/output (gpio) ports ............................................................... 25 1.4.8 infrared (ir) ................................................................................................................. 25 1.4.9 keyboard and mouse controller (kbc) ..................................................................... 26 1.4.10 musical instrument digital interface (midi) port .......................................................... 26 1.4.11 parallel port ............................................................................................................... 27 1.4.12 power and ground ..................................................................................................... 27 1.4.13 protection .................................................................................................................... 28 1.4.14 serial port 1 and serial port 2 ..................................................................................... 28 1.4.15 strap configuration ...................................................................................................... 29 1.4.16 system hardware monitoring ...................................................................................... 29 1.4.17 system wake-up control ............................................................................................ 30 1.4.18 watchdog timer (wdt) ......................................................................................... 30 1.5 internal pull-up and pull-down resistors ............................................................ 31 2.0 device architecture and configuration 2.1 overview ............................................................................................................................... 33 2.2 configuration structure and access ..................................................................... 33 2.2.1 the index-data register pair ...................................................................................... 33 2.2.2 banked logical device registers structure ................................................................ 35 2.2.3 standard logical device configuration register definitions ....................................... 36 2.2.4 standard configuration registers ............................................................................... 38 2.2.5 default configuration setup ........................................................................................ 39 2.2.6 power states .............................................................................................................. .40 2.2.7 address decoding ....................................................................................................... 40 2.3 protection ........................................................................................................................... 40 2.3.1 chassis intrusion detection ......................................................................................... 40 2.3.2 pin configuration lock ................................................................................................ 41 2.3.3 gpio pin function lock .............................................................................................. 41 2.4 power supply control (psc) ......................................................................................... 41 2.5 led operation and states .............................................................................................. 43 2.6 power supply control and led configuration .................................................... 43
table of contents (continued) 6 www.national.com 2.7 register type abbreviations ........................................................................................ 44 2.8 superi/o configuration registers ............................................................................. 44 2.8.1 superi/o id register (sid) .......................................................................................... 45 2.8.2 superi/o configuration 1 register (siocf1) .............................................................. 45 2.8.3 superi/o configuration 2 register (siocf2) .............................................................. 46 2.8.4 superi/o configuration 3 register (siocf3) .............................................................. 47 2.8.5 superi/o configuration 4 register (siocf4) .............................................................. 48 2.8.6 superi/o configuration 5 register (siocf5) .............................................................. 49 2.8.7 superi/o revision id register (srid) ........................................................................ 49 2.8.8 superi/o configuration 8 register (siocf8) .............................................................. 50 2.8.9 superi/o configuration a register (siocfa) ............................................................. 51 2.8.10 superi/o configuration b register (siocfb) ............................................................. 52 2.8.11 superi/o configuration c register (siocfc) ............................................................. 53 2.8.12 superi/o configuration d register (siocfd) ............................................................. 54 2.9 floppy disk controller (fdc) configuration ........................................................ 55 2.9.1 general description ..................................................................................................... 55 2.9.2 logical device 0 (fdc) configuration ......................................................................... 55 2.9.3 fdc configuration register ........................................................................................ 56 2.9.4 drive id register ......................................................................................................... 57 2.10 parallel port configuration ...................................................................................... 58 2.10.1 general description ..................................................................................................... 58 2.10.2 logical device 1 (pp) configuration ............................................................................ 59 2.10.3 parallel port configuration register ............................................................................ 60 2.11 serial port 2 configuration ......................................................................................... 61 2.11.1 general description ..................................................................................................... 61 2.11.2 logical device 2 (sp2) configuration .......................................................................... 61 2.11.3 serial port 2 configuration register ............................................................................ 61 2.12 serial port 1 configuration ......................................................................................... 62 2.12.1 logical device 3 (sp1) configuration .......................................................................... 62 2.12.2 serial port 1 configuration register ............................................................................ 62 2.13 system wake-up control (swc) configuration ..................................................... 63 2.13.1 logical device 4 (swc) configuration ........................................................................ 63 2.14 keyboard and mouse controller (kbc) configuration ..................................... 64 2.14.1 general description ..................................................................................................... 64 2.14.2 logical devices 5 and 6 (mouse and keyboard) configuration .................................. 65 2.14.3 kbc configuration register ........................................................................................ 66 2.15 general-purpose input/output (gpio) ports configuration .......................... 67 2.15.1 general description ..................................................................................................... 67 2.15.2 implementation ........................................................................................................... .67 2.15.3 logical device 7 (gpio) configuration ....................................................................... 68 2.15.4 gpio pin select register ............................................................................................ 69 2.15.5 gpio pin configuration register ................................................................................. 70 2.15.6 gpio event routing register ...................................................................................... 71 2.16 access.bus interface (acb) configuration ............................................................ 72
table of contents (continued) 7 www.national.com 2.16.1 general description ..................................................................................................... 72 2.16.2 logical device 8 (acb) configuration ......................................................................... 72 2.16.3 acb configuration register ........................................................................................ 73 2.17 fan speed control and monitor (fscm) configuration ..................................... 74 2.17.1 general description ..................................................................................................... 74 2.17.2 logical device 9 (fscm) configuration ...................................................................... 74 2.17.3 fan speed control and monitor configuration 1 register ........................................... 75 2.17.4 fan speed control and monitor configuration 2 register ........................................... 76 2.17.5 fan speed control ots configuration register (fcocr) ......................................... 76 2.18 watchdog timer (wdt) configuration ...................................................................... 77 2.18.1 logical device 10 (wdt) configuration ...................................................................... 77 2.18.2 watchdog timer configuration register ................................................................ 77 2.19 game port (gmp) configuration .................................................................................. 78 2.19.1 logical device 11 (gmp) configuration ...................................................................... 78 2.19.2 game port configuration register .............................................................................. 78 2.20 midi port (midi) configuration ...................................................................................... 79 2.20.1 logical device 12 (midi) configuration ....................................................................... 79 2.20.2 midi port configuration register ................................................................................. 79 2.21 voltage level monitor (vlm) configuration .......................................................... 80 2.21.1 logical device 13 (vlm) configuration ....................................................................... 80 2.22 temperature sensor (tms) configuration ............................................................. 80 2.22.1 logical device 14 (tms) configuration ....................................................................... 80 3.0 system wake-up control (swc) 3.1 overview ............................................................................................................................... 81 3.2 functional description .................................................................................................. 82 3.3 event detection ................................................................................................................. 83 3.3.1 modem ring ................................................................................................................ 83 3.3.2 telephone ring ........................................................................................................... 83 3.3.3 keyboard and mouse activity ...................................................................................... 84 3.3.4 ceir address .............................................................................................................. 84 3.3.5 standby general-purpose input events ...................................................................... 84 3.3.6 gpio-triggered events ............................................................................................... 84 3.3.7 software event ............................................................................................................ 84 3.3.8 module irq wake-up event ....................................................................................... 84 3.4 swc registers ..................................................................................................................... 85 3.4.1 swc register map ...................................................................................................... 86 3.4.2 wake-up events status register 0 (wk_sts0) ......................................................... 88 3.4.3 wake-up events status register (wk_sts1) ............................................................ 89 3.4.4 wake-up events enable register (wk_en0) ............................................................. 90 3.4.5 wake-up events enable register 1 (wk_en1) .......................................................... 91 3.4.6 wake-up configuration register (wk_cfg) .............................................................. 92 3.4.7 wake-up events routing to smi enable register 0 (wk_smien0) ........................... 93 3.4.8 wake-up events routing to smi enable register 1 (wk_smien1) ........................... 94
table of contents (continued) 8 www.national.com 3.4.9 wake-up events routing to irq enable register 0 (wk_irqen0) ........................... 95 3.4.10 wake-up events routing to irq enable register 1 (wk_irqen1) ........................... 96 3.4.11 wake-up extension 1 enable register 0 (wk_x1en0) .............................................. 97 3.4.12 wake-up extension 1 enable register 1 (wk_x1en1) .............................................. 98 3.4.13 wake-up extension 2 enable register 0 (wk_x2en0) .............................................. 99 3.4.14 wake-up extension 2 enable register 1 (wk_x2en1) ............................................ 100 3.4.15 wake-up extension 3 enable register 0 (wk_x3en0) ............................................ 101 3.4.16 wake-up extension 3 enable register 1 (wk_x3en1) ............................................ 102 3.4.17 ps/2 keyboard and mouse wake-up events ............................................................ 103 3.4.18 ps/2 protocol control register (ps2ctl) ................................................................. 104 3.4.19 keyboard data shift register (kdsr) ....................................................................... 104 3.4.20 mouse data shift register (mdsr) ........................................................................... 105 3.4.21 ps/2 keyboard key data registers (ps2key0 - ps2key7) .................................... 105 3.4.22 ceir wake-up control register (irwcr) ............................................................... 106 3.4.23 ceir wake-up address register (irwad) .............................................................. 107 3.4.24 ceir wake-up address mask register (irwam) .................................................... 107 3.4.25 ceir address shift register (adsr) ........................................................................ 108 3.4.26 ceir wake-up range 0 registers ........................................................................... 108 3.4.27 ceir wake-up range 1 registers ........................................................................... 109 3.4.28 ceir wake-up range 2 registers ........................................................................... 109 3.4.29 ceir wake-up range 3 registers ........................................................................... 110 3.4.30 standby general-purpose i/o (sbgpio) register overview .................................... 111 3.4.31 standby gpio pin select register (sbgpsel) ........................................................ 114 3.4.32 standby gpio pin configuration register (sbgpcfg) ........................................... 115 3.4.33 standby gpioe/gpie data out register 0 (sb_gpdo0) ........................................ 117 3.4.34 standby gpioe/gpie data in register 0 (sb_gpdi0) ............................................ 117 3.4.35 standby gpos data out register 1 (sb_gpdo1) .................................................. 118 3.4.36 standby gpis data in register 1 (sb_gpdi1) ......................................................... 118 3.5 swc register bitmap ....................................................................................................... 119 4.0 fan speed control 4.1 overview ............................................................................................................................. 122 4.2 functional description ................................................................................................ 122 4.3 fan speed control registers .................................................................................... 123 4.3.1 fan speed control register map .............................................................................. 123 4.3.2 fan speed control pre-scale register (fcpsr) ...................................................... 123 4.3.3 fan speed control duty cycle register (fcdcr) .................................................... 124 4.4 fan speed control bitmap ........................................................................................... 124 5.0 fan speed monitor 5.1 overview ............................................................................................................................. 125 5.2 functional description ................................................................................................ 125 5.3 fan speed monitor registers ..................................................................................... 126 5.3.1 fan speed monitor register map .............................................................................. 126 5.3.2 fan monitor threshold register (fmthr) ................................................................ 127
table of contents (continued) 9 www.national.com 5.3.3 fan monitor speed register (fmspr) ...................................................................... 127 5.3.4 fan monitor control and status register (fmcsr) .................................................. 127 5.4 fan speed monitor bitmap ............................................................................................ 128 6.0 general-purpose input/output (gpio) port 6.1 overview ............................................................................................................................. 129 6.2 basic functionality ........................................................................................................ 130 6.2.1 configuration options ................................................................................................ 130 6.2.2 operation ................................................................................................................... 130 6.3 event handling and system notification .............................................................. 131 6.3.1 event configuration ................................................................................................... 131 6.3.2 system notification .................................................................................................... 131 6.4 gpio port registers ....................................................................................................... 132 6.4.1 gpio pin configuration (gpcfg) register .............................................................. 133 6.4.2 gpio pin event routing (gpevr) register ............................................................. 134 6.4.3 gpio port runtime register map ............................................................................. 134 6.4.4 gpio data out register (gpdo) .............................................................................. 135 6.4.5 gpio data in register (gpdi) .................................................................................. 135 6.4.6 gpio event enable register (gpeven) .................................................................. 136 6.4.7 gpio event status register (gpevst) .................................................................... 136 7.0 watchdog timer (wdt) 7.1 overview ............................................................................................................................. 137 7.2 functional description ................................................................................................ 137 7.3 watchdog timer registers ......................................................................................... 138 7.3.1 watchdog timer register map ............................................................................. 138 7.3.2 watchdog timeout register (wdto) .................................................................. 138 7.3.3 watchdog mask register (wdmsk) .................................................................... 139 7.3.4 watchdog status register (wdst) ...................................................................... 140 7.4 counting down in seconds .......................................................................................... 140 7.5 watchdog timer register bitmap ............................................................................. 140 8.0 access.bus interface (acb) 8.1 overview ............................................................................................................................. 141 8.2 functional description ................................................................................................ 141 8.2.1 data transactions ..................................................................................................... 141 8.2.2 start and stop conditions .......................................................................................... 141 8.2.3 acknowledge (ack) cycle ........................................................................................ 142 8.2.4 acknowledge after every byte rule .......................................................................... 143 8.2.5 addressing transfer formats .................................................................................... 143 8.2.6 arbitration on the bus ................................................................................................ 143 8.2.7 master mode .............................................................................................................. 144 8.2.8 slave mode ................................................................................................................ 146 8.2.9 configuration ............................................................................................................. 146
table of contents (continued) 10 www.national.com 8.3 acb registers .................................................................................................................... 147 8.3.1 acb register map ..................................................................................................... 147 8.3.2 acb serial data register (acbsda) ........................................................................ 147 8.3.3 acb status register (acbst) .................................................................................. 148 8.3.4 acb control status register (acbcst) ................................................................... 149 8.3.5 acb control register 1 (acbctl1) .......................................................................... 150 8.3.6 acb own address register (acbaddr) ................................................................. 151 8.3.7 acb control register 2 (acbctl2) .......................................................................... 151 8.4 acb register bitmap ........................................................................................................ 152 9.0 game port (gmp) 9.1 overview ............................................................................................................................. 153 9.2 functional description ................................................................................................ 153 9.2.1 game device axis position indication ....................................................................... 153 9.2.2 capturing the position ............................................................................................... 154 9.2.3 button status indication ............................................................................................. 154 9.2.4 operation modes ....................................................................................................... 155 9.2.5 operation control ...................................................................................................... 156 9.3 game port registers ..................................................................................................... 157 9.3.1 game port register map ........................................................................................... 157 9.3.2 game port control register (gmpctl) .................................................................... 158 9.3.3 game port legacy status register (gmplst) ......................................................... 159 9.3.4 game port extended status register (gmpxst) ..................................................... 160 9.3.5 game port interrupt enable register (gmpien) ....................................................... 161 9.3.6 game device a x-axis position low byte (gmpaxl) .............................................. 162 9.3.7 game device a x-axis position high byte (gmpaxh) ............................................. 162 9.3.8 game device a y-axis position low byte (gmpayl) .............................................. 162 9.3.9 game device a y-axis position high byte (gmpayh) ............................................. 162 9.3.10 game device b x-axis position low byte (gmpbxl) .............................................. 163 9.3.11 game device b x-axis position high byte (gmpbxh) ............................................. 163 9.3.12 game device b y-axis position low byte (gmpbyl) .............................................. 163 9.3.13 game device b y-axis position high byte (gmpbyh) ............................................. 163 9.3.14 game port event polarity register (gmpepol) ...................................................... 164 9.4 game port bitmap ............................................................................................................. 165 10.0 musical instrument digital interface (midi) port 10.1 overview ............................................................................................................................. 166 10.2 functional description ................................................................................................ 166 10.2.1 internal bus interface unit ......................................................................................... 167 10.2.2 port control and status registers ............................................................................. 167 10.2.3 data buffers and fifos ............................................................................................. 167 10.2.4 midi communication engine ..................................................................................... 167 10.2.5 midi signals routing control logic ........................................................................... 168 10.2.6 operation modes ....................................................................................................... 168 10.2.7 midi port status flags .............................................................................................. 169
table of contents (continued) 11 www.national.com 10.2.8 midi port interrupts ................................................................................................... 170 10.2.9 enhanced midi port features ................................................................................... 171 10.3 midi port registers ........................................................................................................ 172 10.3.1 midi port register map ............................................................................................. 172 10.3.2 midi data in register (mdi) ...................................................................................... 172 10.3.3 midi data out register (mdo) ................................................................................. 172 10.3.4 midi status register (mstat) .................................................................................. 173 10.3.5 midi command register (mcom) ............................................................................ 173 10.3.6 midi control register (mcntl) ................................................................................ 174 10.4 midi port bitmap ................................................................................................................ 175 11.0 voltage level monitor (vlm) 11.1 overview ............................................................................................................................. 176 11.2 functional description ................................................................................................ 176 11.2.1 voltage measurement, channels 0 through 10 ......................................................... 177 11.2.2 thermistor-based temperature measurement, channels 11 to 13 .......................... 178 11.2.3 v os , v high and v low limits, ots and alert output, irq and smi ...................... 178 11.2.4 power-on reset default states ................................................................................ 179 11.2.5 standby mode ........................................................................................................... 179 11.3 analog supply connection ......................................................................................... 179 11.3.1 recommendations ..................................................................................................... 179 11.3.2 reference voltage ..................................................................................................... 180 11.4 register bank overview ............................................................................................... 180 11.5 vlm registers .................................................................................................................... 181 11.5.1 vlm register map ..................................................................................................... 181 11.5.2 voltage event status register 0 (vevsts0) ............................................................ 182 11.5.3 voltage event status register 1 (vevsts1) ............................................................ 182 11.5.4 voltage event to smi register 0 (vevsmi0) ............................................................ 183 11.5.5 voltage event to smi register 1 (vevsmi1) ............................................................ 184 11.5.6 voltage event to irq register 0 (vevirq0) ............................................................ 185 11.5.7 voltage event to irq register 1 (vevirq1) ............................................................ 185 11.5.8 voltage id register (vid) .......................................................................................... 186 11.5.9 voltage conversion rate register (vcnvr) ............................................................ 187 11.5.10 vlm configuration register (vlmcfg) .................................................................... 188 11.5.11 vlm bank select register (vlmbs) ......................................................................... 188 11.5.12 voltage channel configuration and status register (vchcfst) ............................. 189 11.5.13 read channel voltage register (rdchv) ................................................................ 190 11.5.14 channel voltage high limit register (chvh) ........................................................... 190 11.5.15 channel voltage low limit register (chvl) ............................................................ 190 11.5.16 overtemperature shutdown limit register (otsl) ................................................... 190 11.6 vlm register bitmap ........................................................................................................ 191 11.6.1 vlm control and status registers ............................................................................ 191 11.6.2 vlm channel registers ............................................................................................ 191 11.7 usage hints ........................................................................................................................ 192
table of contents (continued) 12 www.national.com 11.7.1 calculating the channel delay .................................................................................. 192 11.7.2 measuring out of range positive and negative voltages ......................................... 193 11.7.3 obtaining the specified vlm/tms accuracy ............................................................. 193 12.0 temperature sensor (tms) 12.1 overview ............................................................................................................................. 194 12.2 functional description ................................................................................................ 194 12.2.1 register bank overview ............................................................................................ 195 12.2.2 t os , t high and t low limits, ots and alert output, irq and smi ...................... 195 12.2.3 alert response read sequence ........................................................................... 196 12.2.4 power-on reset default states ................................................................................ 196 12.2.5 temperature data format ......................................................................................... 197 12.2.6 standby mode ........................................................................................................... 197 12.2.7 diode fault detection ................................................................................................ 197 12.3 tms registers ................................................................................................................... 198 12.3.1 tms register map ..................................................................................................... 198 12.3.2 temperature event status register (tevsts) ......................................................... 199 12.3.3 temperature event to smi register (tevsmi) ......................................................... 200 12.3.4 temperature event to irq register (tevirq) ......................................................... 201 12.3.5 tms configuration register (tmscfg) .................................................................... 202 12.3.6 tms bank select register (tmsbs) ......................................................................... 202 12.3.7 temperature channel configuration and status register (tchcfst) .................... 203 12.3.8 read channel temperature register (rdcht) ........................................................ 204 12.3.9 channel temperature high limit register (chth) ................................................... 204 12.3.10 channel temperature low limit register (chtl) .................................................... 204 12.3.11 channel overtemperature limit register (chotl) .................................................. 204 12.4 tms register bitmap ....................................................................................................... 205 12.4.1 tms control and status registers .......................................................................... 205 12.4.2 tms channel registers ........................................................................................... 205 12.5 usage hints ........................................................................................................................ 206 12.5.1 remote diode selection ............................................................................................ 206 12.5.2 adc noise filtering ................................................................................................... 206 12.5.3 pc board layout ....................................................................................................... 206 12.5.4 twisted pair and shielded cables ............................................................................. 208 12.5.5 obtaining the specified vlm/tms accuracy ............................................................. 208 13.0 legacy functional blocks 13.1 keyboard and mouse controller (kbc) .................................................................. 209 13.1.1 general description ................................................................................................... 209 13.1.2 kbc register map ..................................................................................................... 209 13.1.3 kbc bitmap summary ............................................................................................... 209 13.2 floppy disk controller (fdc) ..................................................................................... 210 13.2.1 general description ................................................................................................... 210 13.2.2 fdc register map ..................................................................................................... 210 13.2.3 fdc bitmap summary ............................................................................................... 211
table of contents (continued) 13 www.national.com 13.3 parallel port .................................................................................................................... 212 13.3.1 general description ................................................................................................... 212 13.3.2 parallel port register map ......................................................................................... 212 13.3.3 parallel port bitmap summary .................................................................................. 213 13.4 uart functionality (sp1 and sp2) ............................................................................... 215 13.4.1 general description ................................................................................................... 215 13.4.2 uart mode register bank overview ....................................................................... 215 13.4.3 sp1 and sp2 register maps for uart functionality ................................................ 216 13.4.4 sp1 and sp2 bitmap summary for uart functionality ........................................... 218 13.5 ir functionality (sp2) ..................................................................................................... 220 13.5.1 general description ................................................................................................... 220 13.5.2 ir mode register bank overview ............................................................................. 220 13.5.3 sp2 register map for ir functionality ...................................................................... 221 13.5.4 sp2 bitmap summary for ir functionality ................................................................ 222 14.0 device characteristics 14.1 general dc electrical characteristics ............................................................... 224 14.1.1 recommended operating conditions ....................................................................... 224 14.1.2 absolute maximum ratings ....................................................................................... 224 14.1.3 capacitance .............................................................................................................. 224 14.1.4 power consumption under recommended operating conditions ............................ 225 14.2 dc characteristics of pins, by i/o buffer types ................................................ 225 14.2.1 input, cmos compatible ........................................................................................... 225 14.2.2 input, pci 3.3v .......................................................................................................... 225 14.2.3 input, smbus compatible .......................................................................................... 225 14.2.4 input, strap pin .......................................................................................................... 226 14.2.5 input, ttl compatible ............................................................................................... 226 14.2.6 input, ttl compatible with schmitt trigger .............................................................. 226 14.2.7 output, pci 3.3v ....................................................................................................... 227 14.2.8 output, totem-pole buffer ......................................................................................... 227 14.2.9 output, open-drain buffer ......................................................................................... 227 14.2.10 input, analog ............................................................................................................. 227 14.2.11 input, analog ............................................................................................................. 227 14.2.12 input, analog ............................................................................................................. 228 14.2.13 output, analog ........................................................................................................... 228 14.2.14 output, analog ........................................................................................................... 228 14.2.15 exceptions ................................................................................................................. 228 14.3 internal resistors ......................................................................................................... 229 14.3.1 pull-up resistor ......................................................................................................... 229 14.3.2 pull-down resistor .................................................................................................... 229 14.4 analog characteristics ............................................................................................... 229 14.4.1 vlm ........................................................................................................................... 229 14.4.2 tms ........................................................................................................................... 230 14.5 ac electrical characteristics .................................................................................. 231 14.5.1 ac test conditions .................................................................................................... 231
table of contents (continued) 14 www.national.com 14.5.2 clock timing .............................................................................................................. 231 14.5.3 lclk and lreset .................................................................................................... 232 14.5.4 lpc and serirq signals ......................................................................................... 233 14.5.5 serial port, sharp-ir, sir and consumer remote control timing ........................... 234 14.5.6 modem control timing .............................................................................................. 235 14.5.7 fdc write data timing ............................................................................................. 235 14.5.8 fdc drive control timing ......................................................................................... 236 14.5.9 fdc read data timing ............................................................................................. 236 14.5.10 standard parallel port timing .................................................................................... 237 14.5.11 enhanced parallel port timing .................................................................................. 237 14.5.12 extended capabilities port (ecp) timing .................................................................. 238
15 www.national.com pc87366 - rev 2.01 1.0 signal/pin connection and description 1.1 connection diagram plastic quad flatpack (pqfp), jedec xxx = three-character identi?er for national data and keyboard rom and/or customer identi?cation code. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 42 41 40 39 pc87366-xxx/vla pd7 vss vbat mtr0 slct dir step wd a t a drate0 trk0 pe wga te rd a t a wp densel index gpio17/ dr1/irsl3 63 62 61 60 43 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 31 32 33 34 35 36 37 38 vdd vsb pwureq gpio16/ mtr1/irsl2 dr0 gpio34/fanout2 gpio01/fanout1 busy_ w ait hdsel dskchg a ck err afd_ dstrb pd1 stb_ write init pd6 pd5 pd4 pd3 slin_ astrb pd2 vss pd0 gpio00/fanin1 gpio33/fanin2 vdd vss vdd vss vdd chasi gpioe1/ o ts1 gpioe2/ o ts2/led1 lad1 lad3 lad2 lreset lclk lframe lad0 ldrq serirq gpio32/p16/irsl1 dtr1_bout1/baddr ri1 dcd1 sout1/psldc0 dsr1 sin1 r ts1/test cts1 dtr2_bout2/psonpol ri2 dcd2 sout2/psldc1 dsr2 sin2 r ts2 cts2 gpio13/sda gpio14/ wdo kbdat kbclk mclk mdat kbrst/gpio06 ga20/gpio07 order number pc87366-xxx/vla see ns package number vla128a gpioe3/led2 gpioe5/ chaso gpio03/fanout0 gpio02/fanin0 gpie6/irrx2_irsl0 gpie7/irrx1 gpo15/irtx gpio10/ smi gpioe4/ ring/ alarm gpio05/p17 gpio04/p12 gpio11 gpio12/scl clkin gpioe0 gpio27/joybbtn1 gpio25/joyby gpio26/joybbtn0 gpio24/joybx gpio23/joyabtn1 gpio21/joyay gpio22/joyabtn0 gpio20/joyax gpio30/mdtx gpio31/mdrx avi5 avi4 avdd vref avi6 d2p d2n/ts3 d1p/ts2 d1n/ts1 avss avi3 avi2 slps5/avi0 pson /gpos1 pwbt out/gpos0 pwbtin/gpis2 slps3 avi1
1.0 signal/pin connection and description (continued) 16 www.national.com 1.2 buffer types and signal/pin directory table 2 i s a n alphabetical list of all signals, cross-referenced to additional information for detailed functional descriptions, electrical dc characteristics and pin multiplexing. the signal dc characteristics are denoted by a buffer type symbol, de- scribed briefly below and in further detail in section 14.2. the pin multiplexing information refers to two different types of multiplexing: l mux - multiplexed, denoted by a slash (/) between pins in the diagram i n section 1.1. pins are shared between two different functions. each function is associated with different board connectivity. normally, the function selection is de- termined by the board design and cannot be changed dynamically. the multiplexing options must be con?gured by the bios upon power-up in order to comply with the board implementation. l mm - multiple mode, denoted by an underscore (_) between pins in the diagram i n section 1.1. pins have two o r more modes of operation within the same function. these modes are associated with the same external (board) con- nectivity. mode selection may b e controlled by the device driver through the registers of the functional block and do not require a special bios setup upon power-up. these pins are not considered multiplexed pins from the superi/o con?guration perspective. the mode selection method (registers and bits), as well as the signal speci?cation in each mode, are described within the functional description of the relevant functional block. table 2. signal/pin directory table 1. buffer types symbol description in an# input, analog type number in c input, cmos compatible in pci input, pci 3.3v in sm input, smbus compatible in strp input, strap pin with weak pull-down during strap time in t input, ttl compatible in ts input, ttl compatible with schmitt trigger in ulr input, with serial ul resistor o an# output, analog type number o pci output, pci 3.3v o p/n output, push-pull buffer that is capable of sourcing p ma and sinking n ma od n output, open-drain output buffer that is capable of sinking n ma pwr power pin gnd ground pin signal pin(s) functional group dc characteristics mux name section buffer type section a ck 79 parallel port 1.4.11 in t 14.2.5 afd_ dstrb 93 parallel port 1.4.11 od 14, o 14/14 14.2.9, 14.2.8 mm alarm 27 hardware monitoring 1.4.16 od 6 14.2.9 mux astrb see slin_ astrb avi0 37 hardware monitoring 1.4.16 in an1 14.2.10 mux avi1-6 38-43 hardware monitoring 1.4.16 in an1 14.2.10 av dd 44 power and ground 1.4.12 pwr n/a av ss 45 power and ground 1.4.12 agnd n/a baddr 101 strap con?guration 1.4.15 in strp 14.2.4 mux bout1 see dtr1_bout1
1.0 signal/pin connection and description (continued) 17 www.national.com bout2 see dtr2_bout2 busy_ w ait 78 parallel port 1.4.11 in t 14.2.5 mm chasi 29 protection 1.4.13 in c 14.2.1 chaso 28 protection 1.4.13 od 6 14.2.9 mux clkin 22 clock 1.4.3 in t 14.2.5 cts1 100 serial port 1 1.4.14 in ts 14.2.6 cts2 108 serial port 2 1.4.14 in ts 14.2.6 dcd1 95 serial port 1 1.4.14 in ts 14.2.6 dcd2 103 serial port 2 1.4.14 in ts 14.2.6 densel 75 fdc 1.4.5 o 2/12 14.2.8 dir 68 fdc 1.4.5 od 12, o 2/12 14.2.9, 14.2.8 d1n d2n 47 49 hardware monitoring 1.4.16 in an3 14.2.12 d1p d2p 48 50 hardware monitoring 1.4.16 in an2 14.2.11 dr0 70 fdc 1.4.5 od 12 ,o 2/12 14.2.9, 14.2.8 dr1 71 fdc 1.4.5 od 12 ,o 2/12 14.2.9, 14.2.8 mux drate0 74 fdc 1.4.5 o 3/6 14.2.8 dskchg 60 fdc 1.4.5 in t 14.2.5 dsr1 96 serial port 1 1.4.14 in ts 14.2.6 dsr2 104 serial port 2 1.4.14 in ts 14.2.6 dstrb see afd_ dstrb dtr1_bout1 101 serial port 1 1.4.14 o 3/6 14.2.8 mux, mm dtr2_bout2 109 serial port 2 1.4.14 o 3/6 14.2.8 mux, mm err 91 parallel port 1.4.11 in t 14.2.5 fanin0 4 fan speed 1.4.4 in ts 14.2.6 mux fanin1 2 fan speed 1.4.4 in ts 14.2.6 mux fanin2 128 fan speed 1.4.4 in ts 14.2.6 mux fanout0 5 fan speed 1.4.4 o 2/14 14.2.8 mux fanout1 3 fan speed 1.4.4 o 2/14 14.2.8 mux fanout2 1 fan speed 1.4.4 o 2/14 14.2.8 mux ga20 (p21) 9 kbc 1.4.9 in t ,od 2 14.2.5, 14.2.9 mux gpie6-7 58-59 system wake-up 1.4.17 in ts 14.2.6 mux gpio00-07 2-9 gpio port 1.4.7 in ts ,od 6 ,o 3/6 14.2.6, 14.2.9, 14.2.8 mux gpio10 gpio11-14 gpo15 gpio16-17 21 53-56 57 69, 71 gpio port 1.4.7 in ts ,od 6 ,o 3/6 14.2.6, 14.2.9, 14.2.8 mux gpio20-27 117-124 gpio port 1.4.7 in ts ,od 6 ,o 3/6 14.2.6, 14.2.9, 14.2.8 mux gpio30-33 gpio34 125-128 1 gpio port 1.4.7 in ts ,od 6 ,o 3/6 14.2.6, 14.2.9, 14.2.8 mux gpioe0-1 23-24 system wake-up 1.4.17 in ts ,od 6 ,o 3/6 14.2.6, 14.2.9, 14.2.8 signal pin(s) functional group dc characteristics mux name section buffer type section
1.0 signal/pin connection and description (continued) 18 www.national.com gpioe2-5 25-28 system wake-up 1.4.17 in ts ,od 6 ,o 3/6 14.2.6, 14.2.9, 14.2.8 mux gpis2 35 system wake-up 1.4.17 in ts 14.2.6 mux gpos0-1 33-34 system wake-up 1.4.17 od 6 ,o 3/6 14.2.9, 14.2.8 mux hdsel 61 fdc 1.4.5 od 12 ,o 2/12 14.2.9, 14.2.8 index 73 fdc 1.4.5 in t 14.2.5 init 89 parallel port 1.4.11 od 14 ,o 14/14 14.2.9, 14.2.8 irrx1 59 infrared 1.4.8 in ts 14.2.6 mux irrx2_irsl0 58 infrared 1.4.8 in ts ,o 3/6 14.2.6, 14.2.8 mux, mm irsl1 127 infrared 1.4.8 in t ,o 3/6 14.2.5, 14.2.8 mux irsl2 69 infrared 1.4.8 in t ,o 3/6 14.2.5, 14.2.8 mux irsl3 71 infrared 1.4.8 in t 14.2.5 mux irtx 57 infrared 1.4.8 o 6/12 14.2.8 mux joyabtn0 119 game port 1.4.6 in ts 14.2.6 mux joyabtn1 120 game port 1.4.6 in ts 14.2.6 mux joyax 117 game port 1.4.6 in ts, od 12 14.2.6, 14.2.9 mux joyay 118 game port 1.4.6 in ts, od 12 14.2.6, 14.2.9 mux joybbtn0 123 game port 1.4.6 in ts 14.2.6 mux joybbtn1 124 game port 1.4.6 in ts 14.2.6 mux joybx 121 game port 1.4.6 in ts, od 12 14.2.6, 14.2.9 mux joyby 122 game port 1.4.6 in ts, od 12 14.2.6, 14.2.9 mux kbclk 111 kbc 1.4.9 in ts ,od 14 14.2.6, 14.2.9 kbdat 112 kbc 1.4.9 in ts ,od 14 14.2.6, 14.2.9 kbrst (p20) 8 kbc 1.4.9 in ts ,od 2 14.2.6, 14.2.9 mux lad0-3 15-18 bus interface 1.4.2 in pci ,o pci 14.2.2, 14.2.7 led1, led2 25, 26 system wake-up 1.4.17 o 12/12 14.2.8 mux lclk 11 bus interface 1.4.2 in pci 14.2.2 ldrq 13 bus interface 1.4.2 o pci 14.2.7 lframe 14 bus interface 1.4.2 in pci 14.2.2 lreset 10 bus interface 1.4.2 in pci 14.2.2 mclk 113 kbc 1.4.9 in ts ,od 14 14.2.6, 14.2.9 mdat 114 kbc 1.4.9 in ts ,od 14 14.2.6, 14.2.9 mdrx 126 midi port 1.4.10 in ts 14.2.6 mux mdtx 125 midi port 1.4.10 o 3/6 14.2.8 mux mtr0 72 fdc 1.4.5 od 12 ,o 2/12 14.2.9, 14.2.8 mtr1 69 fdc 1.4.5 od 12 ,o 2/12 14.2.9, 14.2.8 mux o ts1 o ts2 24 25 hardware monitoring 1.4.16 od 6 14.2.9 mux p12, p16, p17 6,127, 7 kbc 1.4.9 in t ,od 2 14.2.5, 14.2.9 mux signal pin(s) functional group dc characteristics mux name section buffer type section
1.0 signal/pin connection and description (continued) 19 www.national.com pd7-5 pd4-3, pd2, pd1 pd0 80-82 85-86 88, 90 92 parallel port 1.4.11 in t ,o 14/14 14.2.5, 14.2.9, 14.2.8 pe 77 parallel port 1.4.11 in t 14.2.5 psldc0 99 strap con?guration 1.4.15 in strp 14.2.4 mux psldc1 107 strap con?guration 1.4.15 in strp 14.2.4 mux pson 34 system wake-up 1.4.17 od 12 ,o 4/4 14.2.9, 14.2.8 mux psonpol 109 strap con?guration 1.4.15 in strp 14.2.4 mux pwbtin 35 system wake-up 1.4.17 in ts 14.2.6 mux pwbt out 33 system wake-up 1.4.17 od 12 14.2.9 mux pwureq 32 system wake-up 1.4.17 od 6 14.2.9 rd a t a 6 2 fdc 1.4.5 in t 14.2.5 ri1 102 serial port 1 1.4.14 in ts 14.2.6 ri2 110 serial port 2 1.4.14 in ts 14.2.6 ring 27 system wake-up 1.4.17 in ts 14.2.6 mux r ts1 98 serial port 1 1.4.14 o 3/6 14.2.8 mux r ts2 106 serial port 2 1.4.14 o 3/6 14.2.8 scl 54 acb 1.4.1 in t ,od 6 ,o 3/6 14.2.5, 14.2.9, 14.2.8 mux sda 5 5 acb 1.4.1 in t ,od 6 ,o 3/6 14.2.5, 14.2.9, 14.2.8 mux serirq 12 bus interface 1.4.2 in pci ,o pci 14.2.2, 14.2.7 sin1 97 serial port 1 1.4.14 in ts 14.2.6 sin2 105 serial port 2 1.4.14 in ts 14.2.6 slct 76 parallel port 1.4.11 in t 14.2.5 slin_ astrb 87 parallel port 1.4.11 od 14 ,o 14/14 14.2.9, 14.2.8 mm slps3, 5 36,37 system wake-up 1.4.17 in ts 14.2.6 mux ( slps3) smi 21 bus interface 1.4.2 od 12 14.2.9 mux sout1 99 serial port 1 1.4.14 o 3/6 14.2.8 mux sout2 107 serial port 2 1.4.14 o 3/6 14.2.8 mux step 67 fdc 1.4.5 od 12 ,o 2/12 14.2.9, 14.2.8 stb_write 94 parallel port 1.4.11 od 14 ,o 14/14 14.2.9, 14.2.8 mm test 98 strap con?guration 1.4.15 in strp 14.2.4 mux trk0 64 fdc 1.4.5 in t 14.2.5 ts1-3 47-49 vlm 1.4.16 in an1 14.2.10 mux v bat 30 power and ground 1.4.12 in ulr n/a v dd 20, 52, 83, 115 power and ground 1.4.12 pwr n/a v ref 46 hardware monitoring 1.4.16 in an2, o an1 14.2.11, 14.2.13 v sb 31 power and ground 1.4.12 pwr n/a v ss 19, 51, 84, 116 power and ground 1.4.12 gnd n/a w ait see busy_ w ait signal pin(s) functional group dc characteristics mux name section buffer type section
1.0 signal/pin connection and description (continued) 20 www.national.com wd a t a 6 6 fdc 1.4.5 od 12 ,o 2/12 14.2.9, 14.2.8 wdo 56 watchdog 1.4.18 od 6 ,o 3/6 14.2.9, 14.2.8 mux wga te 65 fdc 1.4.5 od 12 ,o 2/12 14.2.9, 14.2.8 wp 63 fdc 1.4.5 in t 14.2.5 write see stb_ write signal pin(s) functional group dc characteristics mux name section buffer type section
1.0 signal/pin connection and description (continued) 21 www.national.com 1.3 pin multiplexing the multiplexing options and the associated setup configuration for all pins are described in table 3. a multiplexing option can be chosen on one pin only per group. table 3. pin multiplexing con?guration pin(s) default alternate signal i/o con?guration signal i/o con?guration 1 gpio34 i/o siocf2, bits 1-0 = 0 0 fanout2 o siocf2, bits 1-0 = 0 1 2 gpio00 i/o siocf2, bit 2 = 0 fanin1 i siocf2, bit 2 = 1 3 gpio01 i/o siocf2, bit 3 = 0 fanout1 o siocf2, bit 3 = 1 4 gpio02 i/o siocf2, bit 4 = 0 fanin0 i siocf2, bit 4 = 1 5 gpio03 i/o siocf2, bit 5 = 0 fanout0 o siocf2, bit 5 = 1 6 gpio04 i/o siocf2, bit 6 = 0 p12 i/o siocf2, bit 6 = 1 7 gpio05 i/o siocf2, bit 7 = 0 p17 i/o siocf2, bit 7 = 1 8 kbrst (p20) siocf3, bit 0 = 1 gpio06 i/o siocf3, bit 0 = 0 9 ga20 (p21) siocf3, bit 1 = 1 gpio07 i/o siocf3, bit 1 = 0 21 gpio10 i/o siocf3, bit 2 = 0 smi o siocf3, bit 2 = 1 24 gpioe1 i/o siocfa, bit 0 = 0 o ts1 o siocfa, bit 0 = 1 25 gpioe2 i/o siocfa, bits 2-1 = 0 0 1 led1 o siocfa, bits 2-1 = 0 1 o ts2 o siocfa, bits 2-1 = 1 0 26 gpioe3 i/o siocfa, bit 3 = 0 1 led2 o siocfa, bit 3 = 1 27 gpioe4 i/o siocfa, bits 5-4 = 0 0 ring i siocfa, bits 5-4 = 0 1 alarm o siocfa, bits 5-4 = 1 0 28 gpioe5 i/o siocfa, bit 6 = 0 chaso o siocfa, bit 6 = 1 33-35, 37 pwbt out pson pwbtin slps5 o o i i siocfa, bit 7 = 0 1 gpos0 gpos1 gpis2 avi0 0 0 i i siocfa, bit 7 = 1 1 47 d1n i siocfb, bit 6 = 0 ts1 i siocfb, bit 6 = 1 48 d1p o siocfb, bit 6 = 0 ts2 i siocfb, bit 6 = 1 49 d2n i siocfb, bit 6 = 0 ts3 i siocfb, bit 6 = 1 54 gpio12 i/o siocf3, bit 5 = 0 scl i/o siocf3, bit 5 = 1 55 gpio13 i/o siocf3, bit 5 = 0 s da i/o siocf3, bit 5 = 1 56 gpio14 i/o siocf3, bit 6 = 0 wdo o siocf3, bit 6 = 1 57 gpo15 o siocf3, bit 7 = 0 i rtx o siocf3, bit 7 = 1 58 gpie6 i siocfb, bit 0 = 0 irrx2_irsl0 i/o siocfb, bit 0 = 1 59 gpie7 i siocfb, bit 1 = 0 irrx1 i siocfb, bit 1 = 1 69 gpio16 i/o siocf4, bits 1-0 = 0 0 mtr1 o siocf4, bits 1-0 = 0 1 irsl2 i/o siocf4, bits 1-0 = 1 0 71 gpio17 i/o siocf4, bits 3-2 = 0 0 dr1 o siocf4, bits 3-2 = 0 1 irsl3 i siocf4, bits 3-2 = 1 0 117 gpio20 i/o siocf4, bit 4 = 0 j oyax i/o siocf4, bit 4 = 1 118 gpio21 i/o siocf4, bit 4 = 0 j oyay i/o siocf4, bit 4 = 1 119 gpio22 i/o siocf4, bit 4 = 0 j oyabtn0 i siocf4, bit 4 = 1 120 gpio23 i/o siocf4, bit 4 = 0 j oyabtn1 i siocf4, bit 4 = 1
1.0 signal/pin connection and description (continued) 22 www.national.com 121 gpio24 i/o siocf4, bit 4 = 0 j oybx i/o siocf4, bit 4 = 1 122 gpio25 i/o siocf4, bit 4 = 0 j oyby i/o siocf4, bit 4 = 1 123 gpio26 i/o siocf4, bit 4 = 0 j oybbtn0 i siocf4, bit 4 = 1 124 gpio27 i/o siocf4, bit 4 = 0 j oybbtn1 i siocf4, bit 4 = 1 125 gpio30 i/o siocf4, bit 5 = 0 mdtx o siocf4, bit 5 = 1 126 gpio31 i/o siocf4, bit 5 = 0 mdrx i siocf4, bit 5 = 1 127 gpio32 i/o siocf4, bits 7,6 = 0 0 p16 i/o siocf4, bits 7,6 = 0 1 irsl1 i/o siocf4, bits 7,6 = 1 0 128 gpio33 i/o siocf5, bits 1-0=0 fanin2 i siocf5, bits 1-0 = 1 0 1. the signal selected on each pin is determined during v sb power-up by the psldc0,1 straps. pin(s) default alternate signal i/o con?guration signal i/o con?guration
1.0 signal/pin connection and description (continued) 23 www.national.com 1.4 detailed signal/pin descriptions this section describes all signals. signals are organized in functional groups. 1.4.1 access.bus interface (acb) 1.4.2 bus interface 1.4.3 clock 1.4.4 fan speed control and monitor (fscm) 1.4.5 floppy disk controller (fdc) signal pin(s) i/o buffer type power well description scl 54 i/o in sm /od 6 v dd access.bus clock signal. an internal pull-up is optional, depending upon the access.bus con?guration register. sda 5 5 i/o in sm /od 6 v dd access.bus data signal. an internal pull-up is optional, depending upon the access.bus con?guration register. signal pin(s) i/o buffer type power well description lad0-3 15-18 i/o in pci /o pci v dd lpc address-data. multiplexed command, address bi- directional data and cycle status. lclk 11 i in pci v dd lpc clock . p ractically, the pci clock (up to 33 mhz). ldrq 13 o o pci v dd lpc dma request . encoded dma request for lpc i/f. lframe 14 i in pci v dd lpc frame . l ow pulse indicates the beginning of new lpc cycle or termination of a broken cycle. lreset 10 i in pci v dd lpc reset. practically, the pci system reset. serirq 12 i/o in pci /o pci v dd serial irq. the interrupt requests are serialized over a single pin, where each internal irq signal is delivered during a designated time slot. smi 21 od od 12 v dd system management interrupt. signal pin(s) i/o buffer type power well description clkin 22 i in t v dd clock in. 48 mhz clock input. signal pin(s) i/o buffer type power well description fanin0 fanin1 fanin2 4 2 128 i in ts v dd fan inputs. used to feed the fans tachometer pulse to the fan speed monitor. the rising edge indicates the completion of a half (or full) revolution of the fan. fanout0 fanout1 fanout2 5 3 1 o o 2/14 v dd fan outputs. pulse width modulation (pwm) signals, used to control the speed of cooling fans by controlling the voltage supplied to the fans motor. signal pin(s) i/o buffer type power well description densel 75 o o 2/12 v dd density select. indicates that a high fdc density data rate (500 kbps or 1 mbps) or a l ow density data rate (250 or 300 kbps) is selected. densel polarity is controlled by bit 5 o f the fdc configuration register. dir 68 o od 12 ,o 2/12 v dd direction. determines the direction of the floppy disk drive (fdd) head movement (active = step in, inactive = step out) during a seek operation. during reads or writes, dir is inactive.
1.0 signal/pin connection and description (continued) 24 www.national.com dr0 70 o od 12 ,o 2/12 v dd drive select 0. decoded drive select output signal. dr0 is controlled by bit 0 o f the digital output register (dor). dr1 71 o od 12 ,o 2/12 v dd drive select 1. decoded drive select output signal. dr0 is controlled by bit 1 o f the digital output register (dor). drate0 74 o o 3/6 v dd data rate 0. reflects the value of bit 0 o f the configuration control register (ccr) or the data rate select register (dsr), whichever was w ritten to last. output from the pin is push-pull buffered. dskchg 60 i in t v dd disk change. indicates if the drive door has been opened. the state of this pin is stored in the digital input register (dir). this pin can also be configured as the rgate data separator diagnostic input signal via the mode command. hdsel 61 o od 12 ,o 2/12 v dd head select. determines which side of the fdd is accessed. active low selects side 1, inactive selects side 0. index 73 i in t v dd index. indicates the beginning of an fdd track. mtr0 72 o od 12 ,o 2/12 v dd motor select 0. active low, motor enable line for drives 0, controlled by bits d7-4 of the digital output register (dor). mtr1 69 o od 12 ,o 2/12 v dd motor select 1. active low, motor enable lines for drives 1, controlled by bits d7-4 of the digital output register (dor). rd a t a62 i in t v dd read data. raw serial input data stream read from the fdd. step 67 o od 12 ,o 2/12 v dd step. issues pulses to the disk drive at a software programmable rate to move the head during a seek operation. trk0 64 i in t v dd track 0. indicates to the controller that the head of the selected floppy disk drive is at track 0 . wd a t a66 o od 12 ,o 2/12 v dd write data . carries out the pre-compensated serial data that is written to the floppy disk drive. pre-compensation is software selectable. wga te 65 o od 12 ,o 2/12 v dd write gate. enables the write circuitry of the selected disk drive. wgate is designed to prevent glitches during power u p and power d own. this prevents writing to the disk when power i s cycled. wp 63 i in t v dd write protected. indicates that the disk in the selected drive i s write protected. a software programmable con?guration bit (fdc con?guration at index f0h, logical device 0) can force an active write-protect indication to the fdc, regardless of the status of this pin. signal pin(s) i/o buffer type power well description
1.0 signal/pin connection and description (continued) 25 www.national.com 1.4.6 game port 1.4.7 general-purpose input/output (gpio) ports 1.4.8 infrared (ir) signal pin(s) i/o buffer type power well description joyax 117 i/o in ts /od 12 v dd joystick a x-axis. indicates x-axis position of joystick a . joyay 118 i/o in ts /od 12 v dd joystick a y-axis. indicates y-axis position of joystick a . joyabtn0 119 i in ts v dd joystick a button 0. indicates button 0 status of joystick a . joyabtn1 120 i in ts v dd joystick a button 1. indicates button 1 status of joystick a . joybx 121 i/o in ts /od 12 v dd joystick b x-axis. indicates x-axis position of joystick b. joyby 122 i/o in ts /od 12 v dd joystick by-axis. indicates y-axis position of joystick b. joybbtn0 123 i in ts v dd joystick b button 0. indicates button 0 status of joystick b. joybbtn1 124 i in ts v dd joystick b button 1. indicates button 1 status of joystick b. signal pin/s i/o buffer type power well description gpio00-07 2-9 i/o in ts / od 6 ,o 3/6 v dd general-purpose i/o port 0, bits 0-7. each pin is configured in- dependently as input or i/o, with or without static pull-up and with either open-drain or push-pull output type. the port support inter- rupt assertion and each pin can be enabled or masked as an inter- rupt source. gpio10 gpio11-14 gpo15 gpio16-17 21 53-56 57 69, 71 i/o in ts / od 6 ,o 3/6 v dd general-purpose i/o port 1, bits 0-7. same as port 0. bit 5 i s output only with low output as default. gpio20-27 117-124 i/o in ts / od 6 ,o 3/6 v dd general-purpose i/o port 2, bits 0-7. similar to port 0 but without the interrupt assertion capability. gpio30-33 gpio34 125-128 1 i/o in ts / od 6 ,o 3/6 v dd general-purpose i/o port 3, bits 0-4. similar to port 0 but without the interrupt assertion capability.bits 5, 6 and 7 are not implemented. signal pin/s i/o buffer type power well description irrx1 59 i in ts v dd ,v sb ir receive 1. primary input to receive serial data from the ir transceiver. monitored during power-off for wake-up event detection. irrx2_irsl0 58 i/o in ts /o 3/6 v dd ,v sb irrx2 - i r receive 2. auxiliary i r receiver input to support a second transceiver. monitored during power-off for wake-up event detection. irsl3-0 ir select . output are used to control the ir transceivers. input for pnp identi?cation of plug-in ir transceiver (dongle). after reset, the dual-function irslx pins wake up in input mode. after the id is read by the ir driver, they m ay be put into output mode. the output mode is controlled by serial port 2. irsl1 127 i/o in t /o 3/6 v dd irsl2 69 i/o in t /o 3/6 v dd irsl3 71 i in t v dd irtx 57 o o 6/12 v dd ir transmit. ir serial output data.
1.0 signal/pin connection and description (continued) 26 www.national.com 1.4.9 keyboard and mouse controller (kbc) 1.4.10 musical instrument digital interface (midi) port signal pin/s i/o buffer type power well description ga20 9 i/o in t /od 2 v dd gate a20. kbc gate a20 (p21) output. kbclk 111 i/o in ts /od 14 v dd ,v sb keyboard clock. transfers the keyboard clock between the superi/o chip and the external keyboard using the ps/2 protocol. this pin is driven by the internal, inverted kbc p26 signal and is connected internally to the t0 signal of the kbc. external pull-up resistor to 5v is required (for ps/2 compliance). the pin is monitored for wake-up event detection. to enable the activity during power off, i t must be pulled up to keyboard and mouse standby voltage. kbdat 112 i/o in ts /od 14 v dd ,v sb keyboard data. transfers the keyboard data between the superi/o chip and the external keyboard using the ps/2 protocol. this pin is driven by the internal, inverted kbc p27 signal and is connected internally to kbc p10. external pull-up resistor to 5v is required (for ps/2 compliance). the pin is monitored for wake-up event detection. to enable the activity during power off, i t must be pulled up to keyboard and mouse standby voltage. kbrst 8 i/o in t /od 2 v dd kbd reset. keyboard reset (p20) output. mclk 113 i/o in ts /od 14 v dd ,v sb mouse clock. transfers the mouse clock between the superi/o chip and the external keyboard using the ps/2 protocol. this pin is driven by the internal, inverted kbc p23 signal and is connected internally to kbc t1. external pull-up resistor to 5v is required (for ps/2 compliance). the pin is monitored for wake-up event detection. to enable the activity during power off, i t must be pulled up to keyboard and mouse standby voltage. mdat 114 i/o in ts /od 14 v dd ,v sb mouse data. transfers the mouse data between the superi/o chip and the external keyboard using the ps/2 protocol. this pin is driven by the internal, inverted kbc p22 signal and is connected internally to kbc p11. external pull-up resistor to 5v is required (for ps/2 compliance). the pin is monitored for wake-up event detection. to enable the activity during power off, i t must be pulled up to keyboard and mouse standby voltage. p12, p16, p17 6,127, 7 i/o in t /od 2 v dd i/o port. kbc open-drain signal for general-purpose input and output, controlled by kbc ?rmware. signal pin(s) i/o buffer type power well description mdtx 125 o o 3/6 v dd midi transmit. midi serial data output. mdrx 126 i in ts v dd midi receive . midi serial data input.
1.0 signal/pin connection and description (continued) 27 www.national.com 1.4.11 parallel port 1.4.12 power and ground signal pin/s i/o buffer type power well description a ck 79 i in t v dd acknowledge. pulsed low by the printer to indicate that it has received data from the parallel port. afd_ dstrb 93 o od 14 ,o 14/14 v dd afd - automatic feed. when low, instructs the printer to automatically feed a line after printing each line. this pin is in tri-state after a 0 is loaded into the corresponding control register bit. an external 4.7 k w pull-up resistor should be attached to this pin. dstrb - data strobe (epp). active l ow, used in epp mode to denote a data cycle. when the cycle is aborted, dstrb becomes inactive (high). busy_ w ait 78 i in t v dd busy. set high by the printer when it cannot accept another character. wait. in epp mode, the parallel port device uses this active low signal to extend its access cycle. err 91 i in t v dd error. set active low by the printer when it detects an error. init 89 o od 14 ,o 14/14 v dd initialize. when low, initializes the printer. this signal is in tri-state after a 1 is loaded into the corresponding control register bit. use an external 4.7 k w pull-up resistor. pd7-5 pd4-3, pd2, pd1 pd0 80-82 85-86 88, 90 92 i/o in t ,o 14/14 v dd parallel port data. transfer data to and from the peripheral data bus and the appropriate parallel port data register. these signals have a high current drive capability. pe 77 i in t v dd paper end. set high by the printer when it is out of paper. this pin has an internal weak pull-up or pull-down resistor. slct 76 i in t v dd select. set active high by the printer when the printer is selected. slin_ astrb 87 o od 14 ,o 14/14 v dd slin - select input. when low, selects the printer. this signal is in tri-state after a 0 is loaded into the corresponding control register bit. uses an external 4.7 k w pull-up resistor. astrb - a ddress strobe (epp). active l ow, used in epp mode to denote an address or data cycle. when the cycle is aborted, astrb becomes inactive (high). stb_ write 94 o od 14 ,o 14/14 v dd stb - data strobe. when low, indicates to the printer that valid data is available at the printer port. this signal is in tri- state after a 0 is loaded into the corresponding control register bit. an external 4.7 k w pull-up resistor should be employed. write - write strobe. active l ow, used in epp mode to denote an address or data cycle. when the cycle is aborted, write becomes inactive (high). signal pin/s i/o buffer type power well description av ss 45 i agnd - analog ground. av dd 44 i pwr - analog 3.3v power supply provides power t o the analog circuits. v bat 30 i in ulr - battery power supply. provides battery back-up to the system wake-up control registers when v sb is lost (power-fail). the pin is connected to the internal logic through a series resistor for ul protection.
1.0 signal/pin connection and description (continued) 28 www.national.com 1.4.13 protection 1.4.14 serial port 1 and serial port 2 v dd 20, 52, 83, 115 i pwr - main 3.3v power supply. v sb 31 i pwr - standby 3.3v power supply. provides power t o the wake-up control circuitry while the main power supply is turned off. v ss 19, 51, 84, 116 i gnd - ground. signal pin(s) i/o buffer type power well description chasi 29 i in c v pp chassis intrusion input. any change of this pin sets the intrusion detection. for correct operation, this pin must be tied to v ss when it is not used. chaso 28 o od 6 v sb chassis intrusion output. when low, indicates that an intrusion indication is set. signal pin/s i/o buffer type power well description cts1 cts2 100 108 i in ts v dd clear to send. when low, indicates that the modem or other data transfer device is ready to exchange data. dcd1 dcd2 95 103 i in ts v dd data carrier detected. when low, indicates that the modem or other data transfer device has detected the data carrier. dsr1 dsr2 96 104 i in ts v dd data set ready. when low, indicates that the data transfer device, e.g., modem, is ready to establish a communications link. dtr1_ bout1 dtr2_ bout2 101 109 o o 3/6 v dd data terminal ready. when low, indicates to the modem or other data transfer device that the uart is ready to establish a communications link. after a system reset, these pins provide the dtr function and set these signals to inactive high. loopback operation holds them inactive. baud output. provides the associated serial channel baud rate generator output signal if test mode is selected, i.e., bit 7 o f the excr1 register is set. dtr1_bout1 is used also as baddr. ri1 ri2 102 110 i in ts v dd ,v sb ring indicator. when low, indicates that a telephone ring signal has been received by the modem. they are monitored during power-off for wake-up event detection. r ts1 r ts2 98 106 o o 3/6 v dd request to send. when low, indicates to the modem or other data transfer device that the corresponding uart is ready to exchange data. a system reset sets these signals to inactive high, and loopback operation holds them inactive. r ts1 is used also as test. sin1 sin2 97 105 i in ts v dd serial input. receive composite serial data from the communications link (peripheral device, modem or other data transfer device). sout1 sout2 99 107 o o 3/6 v dd serial output. send composite serial data to the communications link (peripheral device, modem or other data transfer device). these signals are set active high after a system reset. signal pin/s i/o buffer type power well description
1.0 signal/pin connection and description (continued) 29 www.national.com 1.4.15 strap configuration 1.4.16 system hardware monitoring signal pin/s i/o buffer type power well description baddr 101 i in strp v dd base address. sampled by the trailing edge of the system reset to determine the base address of the con?guration index-data register pair. during reset, it is pulled down by internal 30 k w resistor. if no pull-up resistor is connected, it is sampled low, setting the index-data pair at 2eh-2fh. connecting a 1 0 k w external pull-up resistor to v dd would make it sample high, setting the index-data pair at 4eh-4fh. psldc0 psldc1 99 107 i in strp v sb 1 1. make sure that the serial port driver is back-drive protected. power supply and led con?guration. if no pull-up resistor is connected to these pins, pins 33-35 and 37 function as pwbt out, pson, pwbtin and slps5,respectively. connecting a 10k external pull-up resistor to v sb causes these pins to function as gpos0, gpos1 and gpis2 and avi0, respectively. psonpol 109 i in strp v sb 1 power supply o n polarity. if no pull-up resistor is connected to this pin, pson is set active l ow with open-drain output. connecting a 10k external pull-up resistor to v sb causes pson to be set to active high with push-pull output. test 98 i in strp v dd test. if sampled high on the trailing edge of system reset, this signal forces the device into test mode. this pin is for national semiconductor use only and should be left unconnected. to put the chip in test mode, connect an external pull-up to this pin. otherwise, leave it unconnected or connected to the uart transceiver. signal pin(s) i/o buffer type power well description alarm 27 o od 6 v sb alarm. alerts on voltage input mismatch. avi0-6 37-43 i in an1 av dd analog voltage inputs. analog inputs of the a/d converter. d1n d2n 47 49 i in an3 av dd diode cathode. diodes 1 and 2 return current sink. must be grounded when not used. d1p d2p 48 50 o o an2 av dd diode anode. diodes 1 and 2 current source. connected to remote discrete diodes. o ts1 o ts2 24 25 o od 6 v sb overtemperature shutdown. indicates that an overtemperature was detected. see section 2.8.9, the superi/o con?guration a register, bit 0, for further details on which pin/s is/are active for remote and local temperature sensing. ts1-3 47-49 i in an1 av dd thermistor sensors. analog inputs. v ref 46 i/o in an2, o an1 av dd reference voltage. provides reference voltage for the on-chip a/d circuits. a n external reference voltage should be connected to this input.
1.0 signal/pin connection and description (continued) 30 www.national.com 1.4.17 system wake-up control 1.4.18 watchdog timer (wdt) signal pin/s i/o buffer type power well description led1 led2 25 26 o o 12/12 v sb led. v sb -powered pins with programmable outputs, each of which can be used to produce a 0 , 0.25, 0.5, 1, 4 h z waveform for led control. gpie6-7 58-59 i in ts v sb general-purpose input event. gpioe0-5 23-28 i/o in ts / od 6 ,o 3/6 v sb general-purpose i/o event. v sb -powered pins. gpis2 35 i in ts v sb general-purpose input standby. v sb -powered pin. gpos0-1 33-34 o od 6 ,o 3/6 v sb general-purpose output standby. v sb -powered pins. pson 34 o o 4 ,od 12 v sb power supply on. active l evel (low o r high via psonpol strap) instructs the main power supply to turn the power on. pson output signal is open-drain when active l ow and push-pull when active high. pwbtin 35 i in ts v sb power button in. active (low) level indicates a user request to turn the power o n o r off. this pin has an internal schmitt-trigger input buffer and debounce protection of at least 16 ms. pwbt out 33 o od 12 v sb power button out. active (low) level serves a s output to the chipset power button input. pwureq 32 o od 6 v sb power-up request. active (low) level indicates that wake-up event has occurred and causes the chipset to turn the power supply on or to exit its current sleep state. the open-drain output must be pulled up to v sb in order to function during power-off. ring 27 i in ts v sb telephone line ring. detection of a pulse train on the ring pin is a wake-up event that can activate the power-up request ( pwureq). the pin has a schmitt-trigger input buffer, p owered by v sb . slps3 36 i in ts v sb sleep state 3, 4 o r 5 . input from this pin is assumed to be driven by the systems acpi controller to indicate the systems p ower state. slps5 37 i in ts v sb sleep state 4 o r 5 . input from this pin is assumed to be driven by the systems acpi controller to indicate the systems p ower state. signal pin/s i/o buffer type power well description wdo 56 o od 6 ,o 3/6 v dd watchdog out. low l evel indicates that the watchdog timer has reached its time-out period without being retriggered. the output type and an optional pull-up are con?gurable.
1.0 signal/pin connection and description (continued) 31 www.national.com 1.5 internal pull-up and pull-down resistors the signals listed in table 4 can optionally support internal pull-up (pu) and/or pull-down (pd) resistors. see section 14.3 for the values of each resistor type. table 4. internal pull-up and pull-down resistors signal pin/s type comments access.bus (acb) scl 54 pu 28 programmable sda 5 5 pu 28 programmable game port (gmp) joyabtn0 119 pu 28 programmable joyabtn1 120 pu 28 programmable joybbtn0 123 pu 28 programmable joybbtn1 124 pu 28 programmable general-purpose input/output (gpio) ports gpio00-07 2-9 pu 28 programmable gpio10 gpio11-14 gpo15 gpio16-17 21 53-56 57 69, 71 pu 28 programmable gpio20-27 117-124 pu 28 programmable gpio30-33 gpio34 125-128 1 pu 28 programmable keyboard and mouse controller (kbc) p12, p16, p17 6,127,7 pu 28 musical instrument digital interface (midi) port mdrx 126 pu 25 programmable strap con?guration baddr 101 pd 60 strap psldc0 99 pd 60 strap psldc1 107 pd 60 strap psonpol 109 pd 60 strap test 98 pd 60 strap parallel port a ck 79 pu 220 afd_ dstrb 93 pu 400 busy_ w ait 78 pd 120 err 91 pu 220 init 89 pu 400 pe 77 pu 220 / pd 120 programmable slct 76 pd 120 slin_ astrb 87 pu 400
1.0 signal/pin connection and description (continued) 32 www.national.com stb_ write 94 pu 400 system wake-up control (swc) gpioe0-5 23-28 pu 28 programmable gpis2 35 pu 220 pson/gpos1 34 pu 28 pwbtin 35 pu 220 pwbt out 33 pu 28 ring 27 pu 28 watchdog timer (wdt) wdo 56 pu 28 programmable signal pin/s type comments
33 www.national.com 2.0 device architecture and con?guration the pc87366 superi/o device comprises a collection of generic and proprietary functional blocks. each functional block is described in a separate chapter in this document. however, some parameters in the implementation of each functional block may vary per superi/o device. this chapter describes the pc87366 structure and provides all logical device specific infor- mation, including special implementation of generic blocks, system interface and device configuration. 2.1 overview the pc87366 consists of 15 logical devices, the host interface and a central set of configuration registers, all built around a central internal bus. the internal bus is similar to an 8-bit isa bus protocol. see figure 1, which illustrates the blocks and related logic. the system interface serves as a bridge between the external lpc interface and the internal bus. it supports 8-bit i/o read, 8-bit i/o write and 8-bit dma transactions, as defined in intels lpc interf ace speci?cation, re vision 1.0 . the central configuration register set supports acpi-compliant pnp configuration. the configuration registers are structured as a subset of the plug and play standard registers, defined in appendix a o f the plug and play isa specification, re vision 1.0a by intel and microsoft. all system resources assigned to the functional blocks (i/o address space, dma channels and irq lines) are configured in, and managed by, the central configuration register set. in addition, some function-specific parameters are configurable through the configuration registers and distributed to the functional blocks through special control signals. 2.2 configuration structure and access the configuration structure is comprised of a set of banked registers that are accessed via a pair of specialized registers. 2.2.1 the index-data register pair access to the superi/o configuration registers is via an index-data register pair, using only two system i/o byte locations. the base address of this register pair is determined during reset, according to the state of the hardware strapping option on the baddr pin. table 5 shows the selected base addresses as a function of baddr. table 5. baddr strapping options the index register is an 8-bit r/w register located at the selected base address (base+0). it is used as a pointer to the con- figuration register file and holds the index of the configuration register that is currently accessible via the data register. read- ing the index register returns the last value written to it (or the default of 00h after reset). the data register is an 8-bit virtual register, used as a data path to any configuration register. accessing the data register actually accesses the configuration register that is currently pointed to by the index register. baddr i/o address index register data register 0 2eh 2fh 1 4eh 4fh
2.0 device architecture and configuration (continued) 34 www.national.com figure 1. pc87366 detailed block diagram keyboard fan speed serial port 1 & mouse controller control & access. internal bus bus control signals interface bus scl sda monitor lclk lreset lad3-0 lframe ldrq serirq clkin system p12,p16,p17 ga20 kbclk kbdat mdat mclk kbrst sin1 sout1 r ts1 dtr1/bout1 cts1 dsr1 dcd1 ri1 with ir irrx1,irrx2 irtx irsl0-2 sin2 sout2 r ts2 dtr2/bout2 cts2 dsr2 dcd2 ri2 serial port 2 irsl3 fanout0-2 fanin0-2 pe slct pd0-7 parallel port drate0 rd a t a wd a t a wga te hdsel dir step trk0 index wp mtr1,0 dr1,0 densel fdc watchdog timer wdo gpio00-07 gpio10-14,16,17 gpio20-27 gpio30-34 gpio ports smi stb_ write afd_ dstrb err init slin_ astrb a ck busy_ w ait wake-up control protection dskchg chaso chasi led1,2 pwureq ring gpie6,7 gpioe0-5 slps3 slps5 pwbt out gpos0,1 gpis2 pwbtin pson baddr psldc0,1 test & control registers con?g psonpol system hardware monitoring alarm avi0-6 d1n,d2n d1p,d2p vref o ts1, 2 gpo15 ts1-3 game joyax joyay joyabtn0 joyabtn1 joybx joyby joybbtn0 joybbtn1 midi interface mdtx mdrx strap con?g
2.0 device architecture and configuration (continued) 35 www.national.com 2.2.2 banked logical device registers structure each functional block is associated with a logical device number (ldn). the configuration registers are grouped into banks, where each bank holds the standard configuration registers of the corresponding logical device. table 6 shows the ldn values of the pc87366 functional blocks. figure 2 shows the structure of the standard configuration register file. the superi/o control and configuration registers are not banked and are accessed by the index-data register pair only, as described above. however, the device control and device configuration registers are duplicated over 15 banks for 15 logical devices. therefore, accessing a specific register in a specific bank is performed by two dimensional indexing, where the ldn register selects the bank (or logical device) and the index register selects the register within the bank. accessing the data register while the index register holds a value of 30h or higher results in a physical access to the logical device configuration registers currently pointed to by the index register, within the logical device currently selected by the ldn register. figure 2. structure of the standard con?guration register file table 6. logical device number (ldn) assignments ldn functional block 00h floppy disk controller (fdc) 01h parallel port (pp) 02h serial port 2 with ir (sp2) 03h serial port 1 (sp1) 04h system wake-up control (swc) 05h keyboard and mouse controller (kbc) - mouse interface 06h keyboard and mouse controller (kbc) - keyboard interface 07h general-purpose i/o (gpio) ports 08h access.bus interface (acb) 09h fan speed control and monitor (fscm) 0ah watchdog timer (wdt) 0bh game port (gmp) 0ch musical instrument digital interface (midi) port 0dh voltage level monitor (vlm) 0eh temperature sensor (tms) 07h 20h 30h 60h 75h feh logical device number register superi/o configuration registers logical device control register standard logical device special (vendor-defined) configuration registers banks 2fh f0h bank select 63h 74h 70h 71h configuration registers (one per logical device) logical device
2.0 device architecture and configuration (continued) 36 www.national.com write accesses to unimplemented registers (i.e., accessing the data register while the index register points to a non-existing register) are ignored and read returns 00h on all addresses except for 74h and 75h (dma configuration registers), which returns 04h (indicating no dma channel is active). the configuration registers are accessible immediately after reset. 2.2.3 standard logical device configuration register definitions unless otherwise noted in tables 7 through 12: l all registers are read/write. l all reserved bits return 0 o n reads, except where noted otherwise. they must not be modi?ed as it may cause un- predictable results. use read-modify-write to prevent the values of reserved bits from being changed during write. l write only registers should not use read-modify-write during updates. table 7. standard control registers table 8. logical device activate register table 9. i/o space con?guration registers index register name description 07h logical device number this register selects the current logical device. see table 6 for valid numbers. all other values are reserved. 20h - 2fh superi/o con?guration superi/o con?guration registers and id registers index register name description 30h activate bit 0 - logical device activation control 0: disabled 1: enabled bits 7-1 - reserved index register name description 60h i/o port base address bits (15-8) descriptor 0 indicates selected i/o lower limit address bits 15-8 for i/o descriptor 0. 61h i/o port base address bits (7-0) descriptor 0 indicates selected i/o lower limit address bits 7-0 for i/o descriptor 0. 62h i/o port base address bits (15-8) descriptor 1 indicates selected i/o lower limit address bits 15-8 for i/o descriptor 1. 63h i/o port base address bits (7-0) descriptor 1 indicates selected i/o lower limit address bits 7-0 for i/o descriptor 1.
2.0 device architecture and configuration (continued) 37 www.national.com table 10. interrupt con?guration registers table 11. dma con?guration registers table 12. special logical device con?guration registers index register name description 70h interrupt number and wake-up on irq enable sets irq, indicates the selected interrupt number and enables wake-up on irq. bit 4 - enables wake-up on the irq of the logical device. when enabled, irq assertion triggers a wake-up event. 0: disabled (default) 1: enabled bits 3-0 select the interrupt number. a value of 1 selects irql1. a value of 15 selects irql15. irql0 is not a valid interrupt selection and represent no interrupt selection. note : i f the bios routine that sets irq does not use a read-modify-write sequence, i t might reset bit 4. to ensure that the system wakes u p, the bios must set bit 4 before the system goes to sleep. 71h interrupt request type select indicates the type and level o f the interrupt request level selected in the previous register. if a logical device supports only one type of interrupt, this register may b e read only. bits 7-2 - reserved. bit 1 - level o f the interrupt request selected in the previous register 0: low polarity 1: high polarity bit 0 - type of interrupt request selected in the previous register 0: edge 1: level index register name description 74h dma channel select 0 indicates selected dma channel for dma 0 o f the logical device (0 - the ?rst dma channel in case of using more than one dma channel). bits 2-0 select the dma channel for dma 0. the valid choices are 0-3, where a value of 0 selects dma channel 0, 1 selects channel 1, etc. a value of 4 indicates that no dma channel is active. the values 5-7 are reserved. 75h dma channel select 1 indicates selected dma channel for dma 1 o f the logical device (1 - the second dma channel in case of using more than one dma channel). bits 2-0 select the dma channel for dma 1. the valid choices are 0-3, where a value of 0 selects dma channel 0, 1 selects channel 1, etc. a value of 4 indicates that no dma channel is active. the values 5-7 are reserved. index register name description f0h-feh logical device con?guration special (vendor-de?ned) con?guration options.
2.0 device architecture and configuration (continued) 38 www.national.com 2.2.4 standard configuration registers figure 3. con?guration register map superi/o control and con?guration registers the superi/o configuration registers at indexes 20h and 27h are mainly used for part identification, global power manage- ment and the selection of pin multiplexing options. for details, see section 2.8. logical device control and con?guration registers a subset of these registers is implemented for each logical device. see functional block description in the following sections. superi/o control and con?guration registers logical device control and one per logical device con?guration registers - index register name 07h logical device number 20h superi/o id 21h superi/o con?guration 1 22h superi/o con?guration 2 23h superi/o con?guration 3 24h superi/o con?guration 4 25h superi/o con?guration 5 26h superi/o con?guration 6 27h superi/o revision id 28h superi/o con?guration 8 2ah superi/o con?guration a 2bh superi/o con?guration b 2ch superi/o con?guration c 2dh superi/o con?guration d 2eh reserved exclusively for national use 30h logical device control (activate) 60h i/o base address descriptor 0 bits 15-8 61h i/o base address descriptor 0 bits 7-0 62h i/o base address descriptor 1 bits 15-8 63h i/o base address descriptor 1 bits 7-0 70h interrupt number and wake-up on irq enable (see note, p. 37) 71h irq type select 74h dma channel select 0 75h dma channel select 1 f0h device speci?c logical device con?guration 1 f1h device speci?c logical device con?guration 2 f2h device speci?c logical device con?guration 3 (some are optional)
2.0 device architecture and configuration (continued) 39 www.national.com control the only implemented control register for each logical device is the activate register at index 30h. bit 0 o f the activate reg- ister controls the activation of the associated function block. activation of the block enables access to the blocks registers and attaches its system resources, which are unused as long as the block is not activated. other effects may apply on a function-specific basis (such as clock enable and active pinout signaling). standard con?guration the standard configuration registers are used to manage the pnp resource allocation to the functional blocks. the i/o port base address descriptor 0 i s a pair of registers at index 60-61h, holding the (first or only) 16-bit base address for the register set of the functional block. an optional 16-bit second base-address (descriptor 1) at index 62-63h is used for logical devices with more than one continuous register set. interrupt number and wake-up on irq enable (index 70h) and irq type select (index 71h) allocate an irq line to the block and control its type. dma channel select 0 (index 74h) allocates a dma channel to the block, where applicable. dma channel select 1 (index 75h) allocates a second dma channel, where applicable. special con?guration the vendor-defined registers, starting at index f0h, are used to control function-specific parameters such as operation modes, power saving modes, pin tri-state, clock rate selection and non-standard extensions to generic functions. 2.2.5 default configuration setup the default configuration setup of the pc87366 can include four reset types, described below. see specific register descrip- tions for the bits affected by each reset type. ? software reset this reset is enabled by bit 1 o f the siocf1 register, which resets all logical devices. a software reset also resets most bits in the superi/o control and configuration registers (see section 2.8 for the bits not affected). this reset does not affect register bits that are locked for write access. ? hardware reset this reset is activated by the assertion of the lreset input. it resets all logical devices, with the exception of the system wake-up control (swc). it also resets all superi/o control and configuration registers, except for those that are battery- backed. ? v pp power-up reset this reset is activated when either v sb or v bat is powered up after both have been off. v pp is an internal voltage which is a combination of v sb and v bat .v pp is taken from v sb if v sb is greater than the minimum (min) value defined in the device characteristics chapter; otherwise, v bat is used as the v pp source. this reset resets all registers whose values are retained by v pp . ? v sb power-up reset this is an internally generated reset that resets the swc, excluding those swc registers whose values are retained by v pp . this reset is activated after v sb is powered up. in the event of a hardware reset, the pc87366 wakes up with the following default configuration setup: the con?guration base address is 2eh or 4eh, according to the baddr strap pin value, as shown in table 5. the keyboard controller (kbc) is active and all other logical devices are disabled, with the exception of the swc, which remains functional but whose registers cannot be accessed. all multiplexed gpio pins, except for pins whose function is controlled by battery-backed registers and pins 8 and 9 (which are controlled by bits 1 and 0 o f the siocf3 register) are con?gured as gpio pins, with an internal static pull- up (default direction is input). in the event of either a hardware or a software reset, the pc87366 wakes up with the following default configuration setup: the legacy devices are assigned with their legacy system resource allocation. the national proprietary functions are not assigned with any default resources and the default values of their base addresses are all 00h.
2.0 device architecture and configuration (continued) 40 www.national.com 2.2.6 power states the following terminology is used in this document to describe the various possible power states: ? power on both v sb and v dd are active. ? power off v sb is active and v dd is inactive. ? power fail both v sb and v dd are inactive. note: the following state is illegal: v dd active and v sb inactive. 2.2.7 address decoding a full 16-bit address decoding is applied when accessing the configuration i/o space as well as the registers of the functional blocks. however, the number of configurable bits in the base address registers varies for each logical device. the lower 1, 2, 3, 4 o r 5 address bits are decoded within the functional block to determine the offset of the accessed register within the logical devices i/o range of 2, 4, 8, 16 or 32 bytes, respectively. the rest of the bits are matched with the base address register to decode the entire i/o range allocated to the logical device. therefore, the lower bits of the base address register are forced to 0 (read only) and the base address is forced to be 2, 4, 8, 16 or 32 byte-aligned, according to the size of the i/o range. the base address of the fdc, serial port 1, serial port 2 with ir and kbc are limited to the i/o address range of 00h to 7fxh only (bits 11-15 are forced to 0). the parallel port base address is limited to the i/o address range of 00h to 3f8h. the addresses of the non-legacy logical devices, including the gmp and the midi, are configurable within the full 16-bit ad- dress range (up to fffxh). in some special cases, other address bits are used for internal decoding (such as bit 2 i n the kbc and bit 10 in the parallel port). the kbc has two i/o descriptors with some implied dependency between them. for more details, see the description of the base address register for each logical device. 2.3 protection the pc87366 provides features to protect the pc at mechanical and software levels. at the mechanical level, the device can detect intrusion to the chassis of the pc. at the software level, the device can be locked to protect configuration bits or alteration of the hardware configuration of the device, as well as internal gpio settings and several types of configuration settings. all protection mechanisms can optionally be used. 2.3.1 chassis intrusion detection the chassis intrusion detection mechanism is based on the state of pin 29, chasi. this pin reflects the status of an external switch that indicates the pc chassis state. bits 4,5 of the siocfb register monitor this pin and provide two types of information. bit 4 reports a previously detected chassis intrusion, defined as any kind of transition on the chasi pin. bit 5 reflects the momentary value of the chasi pin. for further details on the siocfb register, see section 2.8.10. to prevent the chasi pin from detecting a false chassis intrusion, it is implemented with an internal noise filter. a chassis intrusion event can be reported to the host system by either software or hardware. when using software, the sys- tem must read the siocfb register to check if an intrusion event has occurred. when using hardware, the device provides the following means for indicating chassis intrusion: l dedicated output ( chaso). l smi assertion. to use the chaso function, it must first be selected by setting bit 6 o f the siocfa register to 1. thereafter, whenever a chassis intrusion is detected, the chaso pin reflects the value of bit 4 o f the siocfb register. when bit 4 o f this register is set to 1, the chaso pin is asserted (driven low). it is de-asserted when this bit is cleared. to use the smi assertion, it must either be selected on its pin or routed to interrupt request channel 2. to select smi on its pin, set bit 2 o f the siocf3 register to 1 (for further details, see section 2.8.4). to route the smi signal to interrupt request channel 2, set bit 4 o f the siocf5 register to 1 (for further details, see section 2.8.6). in addition, the chassis intrusion event must be routed to the smi signal by setting bit 5 o f the siocf8 register to 1 (for further details, see section 2.8.8). thereafter, whenever a chassis intrusion is detected, the smi signal reflects bit 4 o f the siocfb register. when bit 4 o f this register is set to 1, the smi signal and the selected target indication are asserted (driven low). the smi signal is de-asserted when this bit 4 is cleared.
2.0 device architecture and configuration (continued) 41 www.national.com 2.3.2 pin configuration lock to lock the pin configuration of the pc87366 in order to prevent unwanted changes to hardware configuration, set bit 7 o f the siocf1 register to 1. setting this bit causes all function select configuration bits, including those that are battery backed, to become read only bits. this bit can only be cleared by a hardware reset. 2.3.3 gpio pin function lock the pc87366 is capable of locking the attributes of each gpio or standby gpio pin. the following attributes can be locked: l output enable. l output type. l static pull-up. l driven data. gpio pins are locked per pin by setting the lock bit in the appropriate gpio pin configuration register. when the lock bit is set, the configuration of the associated gpio pin can only be released by a hardware reset. standby gpio pins are locked in the same manner by setting the lock bit in the appropriate standby gpio pin configuration registers. however, once a standby gpio pin is locked, its locked attributes can only be released with a v sb power-up reset. 2.4 power supply control (psc) the pc87366 includes hardware that can be used to ease the systems control over the computers power supply. this hard- ware is implemented as a state machine that determines the required state of the power supply based on several input sig- nals. it also connects to the systems acpi controller to share information about the systems power state via specific interface signals. the psc uses the pin functions slps3, slps5, pwbtin, pwbtout and pson. these functions are optional on their respective pins and must be selected to enable the psc by setting the values of the psldc0,1 strap pins (see table 14). once enabled, the psc can be operated in one of two modes, according to the value of bit 0 (power button mode) of the siocfd register: l acpi mode. l legacy mode. acpi mode when the psc is operated in acpi mode (bit 0 o f the siocfd register is set to 1), the acpi controller of the system controls the systems power supply by means of the slps3 state. when slps3 is set to 0, the power supply turns off; when it is set to 1, the power supply turns on. the state of the pson output signal (either on or off) is identical to the state of the slps3 input signal. the polarity of pson is set by the psonpol strap. the only case in which the psc affects the value of the pson output is when a crowbar condition occurs. a crowbar con- dition is defined as the state in which pson has been active for a certain period of time but the systems power supply re- mains inactive. in this case, pson is forced inactive, and the pwbtout output is pulsed to indicate to the acpi controller that slps3 must be driven low, thus indirectly inactivating pson and preventing a deadlock. for a detailed description of the crowbar mechanism, see crowbar condition on the following page(s). in acpi mode, during regular operation, the pwbtout output is pulsed when either of the following events occurs: l pwbtin is pulsed. l a wake-up event that is routed to pwbt out. a wake-up event that is routed to the power button output can cause pwbtout to be pulsed in acpi mode if one of the following conditions is met: l slps5 is active. l enable power button pulse on s3 (bit 3) of the swc wk_cfg register is set to 1. however, when in acpi mode, pwbtin and pwbtout activity has no effect on the pson output. the power button mech- anism can have an indirect effect on pson only if pwbtout is connected to the power button input of the acpi controller, thus affecting the slps3 signal. legacy mode when the psc is operated in legacy mode (bit 0 o f the siocfd register is set to 0), the pc87366 controls the systems power supply. in this mode, the pson output signal is set by the pc87366 according to the following factors: the state of input signals, the state of the power supply lines, power button activity and certain configuration bits. although the acpi con- troller does not control the systems power supply, it tracks the systems power state. for this purpose, the pc87366 ma-
2.0 device architecture and configuration (continued) 42 www.national.com nipulates the pwbtout so that the acpi controller is always synchronized with the actual state of the pson output. this synchronization mechanism assumes that pwbtout is connected to the power button input of the acpi controller. see a schematic state diagram of the legacy psc mechanism in figure 4. figure 4. legacy power supply control state diagram when v sb is first applied, the psc state machine is initialized to power fail state. in this state, the mechanism waits for the pc87366 to be initialized according to strap options. then the psc enters check resume mode state. in this state, the psc checks if resume to last pson state is enabled. if resume to last pson is enabled, pson immediately resumes the state it was in when v sb was lost. to enable this mech- anism, set bit 2 o f the siocfd register to 1 and program the acpi controller to resume off state ( slps3 = 0 ) after power fail recovery to allow the psc to operate properly. if the last state of pson was off, assuming that the acpi controller also resumed off state, pson is set to inactive and the psc enters off state. if the last state was on, under the same as- sumption, the acpi controller must be notified to change its state to on. this is done by pulsing the pwbtout output. this synchronization pulse is generated when the psc is in synchronize acpi state. if resume last pson state is disabled, the psc enters either on or off state according to the value of the slps3 input, as follows: l if slps3 is low (active, state off), the psc enters off state. l if slps3 is high (inactive, state on), the psc enters on state. since slps3 reflects the state of the acpi controller, the psc actually resumes the current state of the acpi controller. after entering either on or off states, psc moves between these two states on the following conditions: l a falling edge on pwbt out (generated internally) changes the state from on to off or vice versa. l a software power supply off command, writing 1 t o power supply off (bit 1) of the siocfd register, changes the state from on to off. since many wake-up events can activate the pwbtout signal, these events can actually cause the psc to change its state from off to on, thus activating the pson output. as in acpi mode, the crowbar protection mechanism is also active in legacy mode. however, in this mode, when a crowbar condition is detected, the psc returns to off state, thus inactivating the pson output. also, to synchronize the apci con- troller, the pwbtout is pulsed to bring it to the correct state. table 13 summarizes the bit states that affect pson v sb power-up default state. power fail on off synchronize acpi check resume mode vsb power-up reset vsb present and straps sampled resume and last state is off or no resume and acpi is off no resume and acpi is on resume and last state is on synchronization done pwbtout falling edge pwbtout falling edge or software power supply off command
2.0 device architecture and configuration (continued) 43 www.national.com table 13. pson v sb power-up default state crowbar condition a crowbar condition is a situation in which the signal that directly controls the systems power supply is active for a certain duration of time without a power supply response. to prevent this deadlock and enable reactivation of the power supply, a special crowbar mechanism is included in the psc logic. once the pson is activated, assuming the power supply is off, a timer in the psc logic starts counting. if this timer reaches its terminal count before the power supply becomes active, the psc detects a crowbar condition. in this case, pson is deactivated and the psc makes sure that the acpi state of the system is changed to off. the time that causes a crowbar condition is defined as the crowbar timeout. the crowbar timeout of the psc can be pro- grammed to values between 0.5-2.25 seconds. this timeout value is set by writing the appropriate value to bits 4-3 of the siocfd register. for further details, refer to the description of this register in section 2.8.12. 2.5 led operation and states the device supports up to two leds, depending on pin 25 and pin 26 function select (bits 1-2 and bit 3) of the siocfa register. the polarity of both leds is determined by led polarity control (bit 7) of the siocfd register. the device provides modes for software led control when in power-on state. the device also provides modes for hardware led control. this enables the leds to support features such as power and error indication. the leds may be operated in software, hardware1 or hardware 2 modes. these modes are set by led mode control (bits 2 and 3) of the siocfb register. each led can be set to on or off or to blink at different rates by means of bits 0-2 (led1) and bits 3-5 (led2) of the siocfc register. when in power-on state (both v dd and v sb exist), the leds are software controlled. when in power-fail state (no v sb and no v dd ), the leds are off. note, however, that these rules are overridden when using the hardware modes. table 14 shows the effect of hardware modes 1 and 2 on led operation. table 14. effect of hardware modes 1 and 2 on led operation 2.6 power supply control and led configuration a combination of two strap pins (power supply and led configuration 0 and 1, psldc0,1, pins 99 and 107, respectively) determines the configuration of the power supply control pins and leds. both pins 99 and 107 have weak pull-downs and are sampled on v sb power-up reset. table 15 describes how they affect the chip configuration. resume last pson state (siocfd, bit 2) last pson state pson v sb power-up default 10 0 11 1 0 x same as slps3 state mode system state led1 led2 hardware1 (siocfb, bits 3-2=01) v sb power-up reset off 1 h z blink, 50% duty cycle power off (v sb ,nov dd ) software controlled 1 h z blink, 50% duty cycle hardware 2 (siocfb, bits 3-2=10) acpi mode and sleep state 3 software controlled software controlled acpi mode, sleep state 5, bit 6 = 1 i n siocfc register and power supply control enabled software controlled software controlled acpi mode, a ny other con?guration off off legacy mode and power off (no v dd ) off off
2.0 device architecture and configuration (continued) 44 www.national.com table 15. psldc0,1 con?guration options 2.7 register type abbreviations the following abbreviations are used to indicate the register type: l r/w = read/write. l r = read from a speci?c address returns the value of a speci?c register. w rite to the same address is to a different register. l w = w rite. l ro = read only. l r/w1c = read/write 1 t o clear. w riting 1 t o a bit clears it to 0. writing 0 has no effect. 2.8 superi/o configuration registers this section describes the superi/o configuration and id registers (those registers with first level indexes in the range of 20h - 2eh). see table 16 for a summary and directory of these registers. table 16. superi/o con?guration registers psldc0 (pin 99) psldc1 (pin 107) power supply control led2 0 0 enabled (default) not selected (default) 0 1 disabled selected 1 0 disabled not selected 1 1 enabled selected index mnemonic register name power well type section 20h sid superi/o id v dd ro 2.8.1 21h siocf1 superi/o con?guration 1 v dd r/w 2.8.2 22h siocf2 superi/o con?guration 2 v dd r/w 2.8.3 23h siocf3 superi/o con?guration 3 v dd r/w 2.8.4 24h siocf4 superi/o con?guration 4 v dd r/w 2.8.5 25h siocf5 superi/o con?guration 5 v dd r/w 2.8.6 27h srid superi/o revision id v dd ro 2.8.7 28h siocf8 superi/o con?guration 8 v dd r/w 2.8.8 2ah siocfa superi/o con?guration a v pp r/w 2.8.9 2bh siocfb superi/o con?guration b v pp r/w 2.8.10 2ch siocfc superi/o con?guration c v pp r/w 2.8.11 2dh siocfd superi/o con?guration d v pp r/w 2.8.12 2eh reserved exclusively for national use
2.0 device architecture and configuration (continued) 45 www.national.com 2.8.1 superi/o id register (sid) this register contains the identity number of the chip. the pc87366 is identified by the value e9h. location: index 20h type: ro 2.8.2 superi/o configuration 1 register (siocf1) location: index 21h type: varies per bit bit 76543210 name chip id reset 11101001 bit 76543210 name pin function select lock pins 117-127 function select number of dma wait states number of i/o wait states sw reset global device enable reset 00010001 bit description 7 pin function select lock. this bit determines if the bits (located in the siocf1, 2, 3, 4, 5, a and b registers) that select pin functions are read only or read/write. when set to 1, this bit can only be cleared by a hardware reset. 0: bits are r/w 1: bits are ro 6 pins 117-127 function select. this is a ro bit. 0: pins 117-127 function set by siocf4 (default) 1: reserved 5-4 number of dma wait states. this is a r/w bit. bits 5 4 number 0 0 reserved 0 1 two (default) 1 0 six 1 1 twelve 3-2 number of i/o wait states. this is a r/w bit. bits 3 2 number 0 0 zero (default) 0 1 two 1 0 six 1 1 twelve 1 sw reset. read always returns 0. this is a r/w bit. 0: ignored (default) 1: resets all the logical devices that are reset by hardware reset (with the exception of the lock bits) and resets the registers of the swc, vlm and tms 0 global device enable. this bit controls the function enable of all the pc87366 logical devices, except system wake-up control (swc). with the exception of swc, i t allows all logical devices to be disabled simultaneously by writing to a single bit. this is a r/w bit. 0: all logical devices in the pc87366 are disabled, except swc, vlm and tms 1: each logical device is enabled according to its activate register (index 30h) (default)
2.0 device architecture and configuration (continued) 46 www.national.com 2.8.3 superi/o configuration 2 register (siocf2) location: index 22h type: r/w bit 7654 3 210 name pin 7 function select pin 6 function select pin 5 function select pin 4 function select pin 3 function select pin 2 function select pin 1 function select reset 0000 0 000 bit description 7 pin 7 function select. 0: gpio05 (default) 1: p17 6 pin 6 function select. 0: gpio04 (default) 1: p12 5 pin 5 function select. 0: gpio03 (default) 1: fanout0 4 pin 4 function select. 0: gpio02 (default) 1: fanin0 3 pin 3 function select. 0: gpio01 (default) 1: fanout1 2 pin 2 function select. 0: gpio00 (default) 1: fanin1 1-0 pin 1 function select. bits 1 0 function 0 0 gpio34 (default) 0 1 fanout2 1 x reserved
2.0 device architecture and configuration (continued) 47 www.national.com 2.8.4 superi/o configuration 3 register (siocf3) location: index 23h type: varies per bit bit 76543210 name pin 57 function select pin 56 function select pins 54, 55 function select pin 53 function select reserved pin 21 function select pin 9 function select pin 8 function select reset 0 0 0 00011 bit description 7 pin 57 function select. this is a r/w bit. 0: gpo15 (default) 1: irtx 6 pin 56 function select. this is a r/w bit. 0: gpio14 (default) 1: wdo 5 pins 54, 55 function select. this is a r/w bit. 0: gpio12/gpio13 (default) 1: scl/sda 4 pin 53 function select. this is a ro bit. 0: gpio11 (default) 1: reserved 3 reserved. 2 pin 21 function select. this is a r/w bit. 0: gpio10 (default) 1: smi 1 pin 9 function select. this is a r/w bit. 0: gpio07 1: ga20 (p21) (default) 0 pin 8 function select. this is a r/w bit. 0: gpio06 1: kbrst (p20) (default)
2.0 device architecture and configuration (continued) 48 www.national.com 2.8.5 superi/o configuration 4 register (siocf4) location: index 24h type: r/w bit 76543210 name pin 127 function select pins 125,126 function select pins 117-124 function select pin 71 function select pin 69 function select reset 00000000 bit description 7-6 pin 127 function select. bits 7 6 function 0 0 gpio32 (default) 0 1 p16 1 0 irsl1 1 1 reserved 5 pins 125,126 function select. 0: gpio30,31 (default) 1: mdtx, mdrx 4 pins 117-124 function select. 0: gpio20-27 (default) 1: joyax, joyay, joyabtn0, joyabtn1, joybx, joyby, j oybbtn0, joybbtn1 3-2 pin 71 function select. bits 3 2 function 0 0 gpio17 (default) 0 1 dr1 1 0 irsl3 1 1 reserved 1-0 pin 69 function select. bits 1 0 function 0 0 gpio16 (default) 0 1 mtr1 1 0 irsl2 1 1 reserved
2.0 device architecture and configuration (continued) 49 www.national.com 2.8.6 superi/o con?guration 5 register (siocf5) location: index 25h type: varies per bit 2.8.7 superi/o revision id register (srid) this register contains the identity number of the chip revision. srid is incremented on each revision. location: index 27h type: ro bit 76543210 name vid0 and vid1 route select smi to irq2 enable reserved pin 128 function select reset 00000000 bit description 7-5 vid0 and vid1 route select. de?nes the routing of gpio inputs to the vlm vid register. this is a r/w bit. bits 7 6 5 route select 0 0 0 vid0 and vid1 are not routed. 0 0 1 vid4-vid0 are routed from gpio11-13, gpio16, gpio17. only cpu0 is supported. 0 1 0 vid4-vid0 are routed from gpio05, gpio12-14, gpio32. only cpu0 is supported. 0 1 1 when cpu0 is selected: vid4-vid0 are routed from gpio20-24; when cpu1 is selected: vid4-vid0 are routed from gpio25-27, gpio30, gpio31 1 0 0 vid4-vid0 are routed from gpio11-13, gpio16, gpio17; processor select control is routed to gpio14, which is configured as output. other reserved 4 smi to irq2 enable. this is a r/w bit. 0: disabled (default) 1: enabled 3-2 reserved. 1-0 pin 128 function select. this is a r/w bit. bits 1 0 function 0 0 gpio33 (default) 0 1 fanin2 1 x reserved
2.0 device architecture and configuration (continued) 50 www.national.com 2.8.8 superi/o configuration 8 register (siocf8) location: index 28h type: r/w bit 76543210 name vlm to smi enable tms to smi enable chaso to smi enable mouse irq to smi enable kbd irq to smi enable kbd p12 to smi enable gpi to smi enable wdo to smi enable reset 0 0 0 00000 bit description 7 vlm to smi enable. 0: disabled (default) 1: enabled 6 tms to smi enable. 0: disabled (default) 1: enabled 5 chaso to smi enable. 0: disabled (default) 1: enabled: 4 mouse irq to smi enable. 0: disabled (default) 1: enabled 3 kbd irq to smi enable. 0: disabled (default) 1: enabled 2 kbd p12 to smi enable. 0: disabled (default) 1: enabled 1 gpi to smi enable. 0: disabled (default) 1: enabled 0 wdo to smi enable. 0: disabled (default) 1: enabled
2.0 device architecture and configuration (continued) 51 www.national.com 2.8.9 superi/o configuration a register (siocfa) this is a battery-backed register. location: index 2ah type: varies per bit bit 76543210 name pins 33-37 function select pin 28 function select pin 27 function select pin 26 function select pin 25 function select pin 24 function select reset strap 0000000 bit description 7 pins 33-37 function select. this is a ro bit. the function of the pin selected is determined during v sb power- up by the psldc0,1 straps. 0: pwbt out, pson, pwbtin, slps3, slps5 1: gpos0, gpos1, gpis2, slps3, avi0 6 pin 28 function select. this is a r/w bit. 0: gpioe5 (default at v pp power-up reset) 1: chaso 5-4 pin 27 function select. this is a r/w bit. bits 5 4 function 0 0 gpioe4 (default at v pp power-up reset) 0 1 ring 1 0 alarm other reserved 3 pin 26 function select. this is a r/w bit. 0: gpioe3 (default at v pp power-up reset) 1: led2 2-1 pin 25 function select. this is a r/w bit. bits 2 1 function 0 0 gpioe2 (default at v pp power-up reset) 0 1 led1 1 0 ots2 (can be enabled only if ots1 is enabled) other reserved 0 pin 24 function select. 0: gpioe1 (default at v pp power-up reset) 1: ots1. ots1 functionality changes when o ts2 is enabled. the following table summarizes which ots output is affected when an overtemperature is detected by any o f the sources. a y indicates that the pin is active for this condition; an n indicates that it is inactive. source 1 ots pin 2 ots pins o ts1 o ts1 o ts2 remote 1 y y n remote 2 y n y local y y n vlm y y n
2.0 device architecture and configuration (continued) 52 www.national.com 2.8.10 superi/o configuration b register (siocfb) this is a battery-backed register. location: index 2bh type: varies per bit bit 7 6 5 4 3 2 1 0 name reserved pins 47-49 function select intrusion level intrusion status led mode contro l pin 59 function select pin 58 function select reset 0 0 x 1 0 0 0 0 bit description 7 reserved. 6 pins 47-49 function select. 0: pins 47-49 enabled as d1n, d1p and d2n by the tms (default) 1 pins 47-49 enabled as ts1, ts2 and ts3 by the vlm. for further details, see the tms con?guration register setting. 5 intrusion level. this is a ro bit that re?ects the value of pin 29 (chasi)either 0 or 1. 4 intrusion status. write 0 to this bit to clear it. 0: no intrusion 1: intrusion detected (default at v pp power-up reset) 3-2 led mode control. this is a r/w bit. bits 3 2 function 0 0 software mode (default at v pp power-up reset) 0 1 hardware mode 1 (default when power supply control is disabled by psldc0,1 straps) 1 0 hardware mode 2 1 1 reserved 1 pin 59 function select. this is a r/w bit. 0: gpie7 (default at v pp power-up reset) 1: irrx1 0 pin 58 function select. this is a r/w bit. 0: gpie6 (default at v pp power-up reset) 1: irrx2_irsl0
2.0 device architecture and configuration (continued) 53 www.national.com 2.8.11 superi/o configuration c register (siocfc) this is a battery-backed register. location: index 2ch type: r/w bit 76543210 name led configura- tion power led status in s4 or s5 led2 blink rate led1 blink rate reset 00000000 bit description 7 led con?guration. 0: one dual-colored led (default at v pp power-up reset) 1: two leds 6 power led status in s4 or s5. this bit is active only when hardware mode 2 i s selected (bits 2-3 in the siocfb regis- ter). 0: turn off (default at v dd power off) 1: unchanged 5-3 led2 blink rate. bits 5 4 3 rate (hz) duty cycle 0 0 0 off always low 0 0 1 0.25 12.5% 0 1 0 0.5 25% 0 1 1 1 50% 1 1 0 0 2 50% 1 0 1 3 50% 1 1 0 4 50% 1 1 1 o n always high (default at v pp power-up reset) 1. when hardware mode 1 i s selected, this rate is set when v sb is powered up or when v dd becomes inactive while v sb is active. 2-0 led1 blink rate. bits 2 1 0 rate (hz) duty cycle 0 0 0 off always low (default at v pp power-up reset) 0 0 1 0.25 12.5% 0 1 0 0.5 25% 0 1 1 1 50% 1 0 0 2 50% 1 0 1 3 50% 1 1 0 4 50% 1 1 1 o n always high
2.0 device architecture and configuration (continued) 54 www.national.com 2.8.12 superi/o configuration d register (siocfd) this is a battery-backed register. location: index 2dh type: varies per bit bit 76543210 name led polarity control last pson state pson polarity crowbar timeout resume last pson state power supply off power button mode reset 0 0 strap 11000 bit description 7 led polarity control. this is a r/w bit. it determines if the led outputs are active high or active low when they are lit. 0: active high (default at v sb power-up reset) 1: active l ow 6 last power supply on state. this is a r o bit. when operating in legacy mode (bit 0 o f this register is set to 0), this bit reflects the state of the pson pin sampled during the last power failure (no v sb ), regardless of the polarity of pson. 0: off 1: on 5 power supply on polarity. this is a ro bit. the polarity of pson is determined during v sb power-up by the psonpol strap. 4-3 crowbar timeout. this is a r/w bit. bits 5 4 value (seconds) 0 0 0.4 to 0.9 (typical 0.6) 0 1 0.9 to 1.4 (typical 1.1) 1 0 1.4 to 1.9 (typical 1.6) 1 1 1.9 to 2.5 (typical 2.1) (default at v pp power-up reset) note that for any specific condition, there is a minimum gap of 0.25 seconds between the actual high limit of a time- out setting and the low limit of the next time-out setting. 2 resume last power supply on state. this is a r/w bit. when it is set to 1, pson resumes its last state, sampled during the last power failure, after power returns. when this bit is set to 0, the pson state is determined by the slps3 state. 0: slps3 (default at v pp power-up reset) 1: last pson state. for correct operation, the systems acpi controller must be con?gured to resume to off. this enables the power supply control logic to know the state of the chipset acpi state machine after power failure (no v dd and v sb ). 1 power supply off. this is a r/w bit. it always returns 0 when read. when using legacy mode (bit 0 i s set to 0) and setting this bit to 1, this bit inactivates the pson output, thereby shutting off the power supply. 0: no action (default at v pp power-up reset) 1: inactivate pson in legacy mode 0 power button mode. this is a r/w bit. 0: legacy (default at v sb power-up reset) 1: acpi
2.0 device architecture and configuration (continued) 55 www.national.com 2.9 floppy disk controller (fdc) configuration 2.9.1 general description the generic fdc is a standard fdc with a digital data separator and is dp8473 and n82077 software compatible. the pc87366 fdc supports 14 of the 17 standard fdc signals described in the generic floppy disk controller (fdc) chapter, including: l fm and mfm modes are supported. to select either mode, set bit 6 o f the ?rst command byte when writing to/read- ing from a diskette, where: 0 = f m mode 1 = mfm mode l a logic 1 i s returned for all ?oating (tri-state) fdc register bits upon lpc i/o read cycles. exceptions to standard fdc support include: l automatic media sense is not supported (msen0-1 pins are not implemented) l drate1 is not supported. table 17 lists the fdc functional block registers. table 17. fdc registers 2.9.2 logical device 0 (fdc) configuration table 18 lists the configuration registers that affect the fdc. only the last two registers (f0h and f1h) are described here. see sections 2.2.3 and 2.2.4 for descriptions of the others. table 18. fdc con?guration registers offset 1 1. this is the 8-byte aligned fdc base address. mnemonic register name type 00h sra status a ro 01h srb status b ro 02h dor digital output r/w 03h tdr tape drive r/w 04h msr main status r dsr data rate select w 05h fifo data (fifo) r/w 06h n/a x 07h dir digital input r ccr con?guration control w index con?guration register or action type reset 30h activate. see also bit 0 o f the siocf1 register and bit 0 o f the siocf6 register. r/w 00h 60h base address msb register. bits 7-3 (for a15-11) are read only, 00000b. r/w 03h 61h base address lsb register bits 2 and 0 ( for a 2 and a0) are read only, 00b. r/w f2h 70h interrupt number and wake-up on irq enable register (see note, p. 37). r/w 06h 71h interrupt type. bit 1 i s read/write; other bits are read only. r/w 03h 74h dma channel select. r/w 02h 75h report n o second dma assignment. ro 04h f0h fdc con?guration register. r/w 24h f1h drive i d register. r/w 00h
2.0 device architecture and configuration (continued) 56 www.national.com 2.9.3 fdc configuration register this register is reset by hardware to 24h. location: index f0h type: r/w bit 76543210 name reserved tdr register mode densel polarity control reserved write protect pc-at or ps/2 drive mode select reserved tri-state control reset 00100100 required 0 0 bit description 7 reserved. must be 0. 6 tdr register mode. 0: pc-at compatible drive mode; i.e., bits 7-2 of the tdr are 111111b (default) 1: enhanced drive mode 5 densel polarity control. 0: active l ow for 500 kbps or 1 mbps data rates 1: active high for 500 kbps or 1 mbps data rates (default) 4 reserved. must be 0. 3 write protect. this bit allows software to force write protect functionality. when set, writes to the floppy disk drive are disabled. this effect is identical to wp when it is active. 0: write protected according to wp signal (default) 1: write protected regardless of value of wp signal 2 pc-at o r ps/2 drive mode select. 0: ps/2 drive mode 1: pc-at d rive mode (default) 1 reserved. 0 tri-state control. when enabled and the device is inactive, the logical device output pins are in tri-state. 0: disabled (default) 1: enabled
2.0 device architecture and configuration (continued) 57 www.national.com 2.9.4 drive id register this read/write register is reset by hardware to 00h. this register controls bits 5 and 4 o f the tdr register in enhanced mode. location: index f1h type: r/w usage hints: some bios implementations support automatic media sense fdds, in which case bit 5 o f the tdr register in enhanced mode is interpreted as valid media sense when it is cleared to 0. if drive 0 and/or drive 1 d o not support auto- matic media sense, bits 1 and/or 3 o f the drive id register should be set to 1 (to indicate non-valid media sense). when the corresponding drive (0 or 1) is selected, the drive id bit is reflected in bit 5 of the tdr register in enhanced mode. bit 76543210 name reserved drive 1 i d drive 0 i d reset 00000000 bit description 7-4 reserved. 3-2 drive 1 i d. when drive 1 i s accessed, these bits are re?ected on bits 5-4 of the tdr register, respectively. 1-0 drive 0 i d. when drive 0 i s accessed, these bits are re?ected on bits 5-4 of the tdr register, respectively.
2.0 device architecture and configuration (continued) 58 www.national.com 2.10 parallel port configuration 2.10.1 general description the pc87366 parallel port supports all ieee1284 standard communication modes: compatibility (known also as standard or spp), bi-directional (known also as ps/2), fifo, epp (known also as mode 4) and ecp (with an optional extended ecp mode). the parallel port includes two groups of runtime registers, as follows: ? a group of 21 registers at first level offset, sharing 14 entries. three of this registers (at offsets 403h, 404h and 405h) are used only in the extended ecp mode. ? a group of four registers, used only in the extended ecp mode, accessed by a second level offset. the desired mode is selected by the ecr runtime register (offset 402h). the selected mode determines which runtime reg- isters are used and which address bits are used for the base address. see tables 19 and 20 for a listing of all registers, their offset addresses and the associated modes. table 19. parallel port registers at first level offset table 20. parallel port registers at second level offset offset mnemonic mode(s) type register name 00h datar 0,1 r/w data afifo 3 w ecp fifo (address) dtr 4 r/w data (for epp) 01h dsr 0,1,2,3 ro status str 4 ro status (for epp) 02h dcr 0,1,2,3 r/w control ctr 4 r/w control (for epp) 03h addr 4 r/w epp address 04h data0 4 r/w epp data port 0 05h data1 4 r/w epp data port 1 06h data2 4 r/w epp data port 2 07h data3 4 r/w epp data port 3 400h cfifo dfifo tfifo cnfga 2 3 6 7 w r/w r/w ro pp data fifo ecp data fifo test fifo con?guration a 401h cnfgb 7 ro con?guration b 402h ecr 0,1,2,3 r/w extended control 403h eir 1 1. these registers are extended to the standard ieee1284 registers. they are accessi- ble only when enabled by bit 4 o f the parallel port con?guration register (see section 2.10.3). 0,1,2,3 r/w extended index 404h edr 1 0,1,2,3 r/w extended data 405h ear 1 0,1,2,3 r/w extended auxiliary status offset mnemonic type register name 00h control0 r/w extended control 0 02h control2 r/w extended control 1 04h control4 r/w extended control 4 05h pp confg0 r/w con?guration 0
2.0 device architecture and configuration (continued) 59 www.national.com 2.10.2 logical device 1 (pp) configuration table 21 lists the configuration registers that affect the parallel port. only the last register (f0h) is described here. see sec- tions 2.2.3 and 2.2.4 for descriptions of the others. table 21. parallel port con?guration registers index con?guration register or action type reset 30h activate. see also bit 0 o f the siocf1 register. r/w 00h 60h base address msb register. bits 7-3 (for a15-11) are read only, 00000b. bit 2 ( for a10) should be 0b. r/w 02h 61h base address lsb register. bits 1 and 0 (a1 and a0) are read only, 00b. for ecp mode 4 (epp) or when using the extended registers, bit 2 (a2) should also be 0b. r/w 78h 70h interrupt number and wake-up on irq enable register (see note, p. 37). r/w 07h 71h interrupt type bits 7-2 are read only. bit 1 i s a read/write bit. bit 0 i s read only. i t re?ects the interrupt type dictated by the parallel port operation mode. this bit is set to 1 (level interrupt) in extended mode and cleared (edge interrupt) in all other modes. r/w 02h 74h dma channel select. r/w 04h 75h report n o second dma assignment. ro 04h f0h parallel port con?guration register. r/w f2h
2.0 device architecture and configuration (continued) 60 www.national.com 2.10.3 parallel port configuration register this register is reset by hardware to f2h. location: index f0h type: r/w bit 76543210 name parallel port mode select extended register access reserved power mode control tri-state control reset 11110010 bit description 7-5 parallel port mode select. bits 7 6 5 function 0 0 0 spp-compatible mode pd7-0 are always output signals 0 0 1 spp extended mode pd7-0 direction is controlled by software 0 1 0 epp 1.7 mode 0 1 1 epp 1.9 mode 1 0 0 ecp mode (ieee1284 register set), with no support for epp mode 1 0 1 reserved 1 1 0 reserved 1 1 1 ecp mode (ieee1284 register set), with epp mode selectable as mode 4 selection of epp 1.7 or 1.9 in ecp mode 4 is controlled by bit 4 of the control2 configuration register of the parallel port at offset 02h. note : before setting bits 7-5, enable the parallel port and set ctr/dcr (at base address + 2) to c4h. 4 extended register access. 0: registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored). 1: registers at base (address) + 403h, base + 404h and base + 405h are accessible. this option supports run- time con?guration within the parallel port address space. 3-2 reserved. 1 power mode control. when the logical device is active: 0: parallel port clock disabled. ecp modes and epp time-out are not functional when the logical device is active. registers are maintained. 1: parallel port clock enabled. all operation modes are functional when the logical device is active (default). 0 tri-state control. when enabled and the device is inactive, the logical device output pins are in tri-state. 0: disabled (default) 1: enabled
2.0 device architecture and configuration (continued) 61 www.national.com 2.11 serial port 2 configuration 2.11.1 general description serial port 2 includes ir functionality as described in the serial port 2 with ir chapter. 2.11.2 logical device 2 (sp2) configuration table 22 lists the configuration registers that affect the serial port 2. only the last register (f0h) is described here. see sec- tions 2.2.3 and 2.2.4 for descriptions of the others. table 22. serial port 2 con?guration registers 2.11.3 serial port 2 configuration register this register is reset by hardware to 02h. location: index f0h type: r/w index con?guration register or action type reset 30h activate. see also bit 0 o f the siocf1 register and bit 2 o f the siocf6 register. r/w 00h 60h base address msb register. bits 7-3 (for a15-11) are read only, 00000b. r/w 02h 61h base address lsb register. bit 2-0 (for a2-0) are read only, 000b. r/w f8h 70h interrupt number and wake-up on irq enable register (see note, p. 37). r/w 03h 71h interrupt type. bit 1 i s r/w; other bits are read only. r/w 03h 74h dma channel select 0 (rx_dma). r/w 04h 75h dma channel select 1 (tx_dma). r/w 04h f0h serial port 2 con?guration register. r/w 02h bit 76543210 name bank select enable reserved busy indicator power mode control tri-state control reset 00000010 bit description 7 bank select enable. enables bank switching for serial port 2. 0: all attempts to access the extended registers in serial port 2 are ignored (default). 1: enables bank switching for serial port 2. 6-3 reserved. 2 busy indicator. this read only bit can be used by power management software to decide when to power-down the serial port 2 logical device. 0: no transfer in progress (default). 1: transfer in progress. 1 power mode control. when the logical device is active in: 0: low p ower mode serial port 2 clock disabled. the output signals are set to their default states. the ri input signal can be programmed to generate an interrupt. registers are maintained. (unlike active bit in index 3 0 that also prevents access to serial port 2 registers.) 1: normal power mode serial port 2 clock enabled. serial port 2 i s functional when the logical device is active (default). 0 tri-state control. when enabled and the device is inactive, the logical device output pins are in tri-state. one exception is the irtx pin, which is driven to 0 when serial port 2 i s inactive and is not affected by this bit. 0: disabled (default) 1: enabled
2.0 device architecture and configuration (continued) 62 www.national.com 2.12 serial port 1 configuration 2.12.1 logical device 3 (sp1) configuration table 23 lists the configuration registers that affect the serial port 2. only the last register (f0h) is described here. see sec- tions 2.2.3 and 2.2.4 for descriptions of the others. table 23. serial port 1 con?guration registers 2.12.2 serial port 1 configuration register this register is reset by hardware to 02h. location: index f0h type: r/w index con?guration register or action type reset 30h activate. see also bit 0 o f the siocf1 register and bit 3 o f the siocf6 register. r/w 00h 60h base address msb register. bits 7-3 (for a15-11) are read only, 00000b. r/w 03h 61h base address lsb register. bit 2-0 (for a2-0) are read only, 000b. r/w f8h 70h interrupt number and wake-up on irq enable register (see note, p. 37). r/w 04h 71h interrupt type. bit 1 i s r/w; other bits are read only. r/w 03h 74h report n o dma assignment. ro 04h 75h report n o dma assignment. ro 04h f0h serial port 1 con?guration register. r/w 02h bit 76543210 name bank select enable reserved busy indicator power mode control tri-state control reset 00000010 bit description 7 bank select enable. enables bank switching for serial port 1. 0: disabled (default). 1: enabled 6-3 reserved. 2 busy indicator. this read only bit can be used by power management software to decide when to power-down the serial port 1 logical device. 0: no transfer in progress (default). 1: transfer in progress. 1 power mode control. when the logical device is active in: 0: low p ower mode serial port 1 clock disabled. the output signals are set to their default states. the ri input signal can be programmed to generate an interrupt. registers are maintained. (unlike active bit in index 3 0 that also prevents access to serial port 1 registers.) 1: normal power mode serial port 1 clock enabled. serial port 1 i s functional when the logical device is active (default). 0 tri-state control. when enabled and the device is inactive, the logical device output pins are in tri-state. 0: disabled (default) 1: enabled
2.0 device architecture and configuration (continued) 63 www.national.com 2.13 system wake-up control (swc) configuration 2.13.1 logical device 4 (swc) configuration table 24 lists the configuration registers that affect the swc. see sections 2.2.3 and 2.2.4 for a detailed description of these registers. table 24. system wake-up control (swc) con?guration registers index con?guration register or action type reset 30h activate. when bit 0 i s cleared, the registers of this logical device are not accessible. 1 1. the logical device registers are maintained and all wake-up detection mechanisms are functional. r/w 00h 60h base address msb register. r/w 00h 61h base address lsb register. bits 4-0 (for a4-0) are read only, 00000b. r/w 00h 70h interrupt number (see note, p. 37). r/w 00h 71h interrupt type. bit 1 i s read/write. other bits are read only. r/w 03h 74h report n o dma assignment. ro 04h 75h report n o dma assignment. ro 04h
2.0 device architecture and configuration (continued) 64 www.national.com 2.14 keyboard and mouse controller (kbc) configuration 2.14.1 general description the kbc is implemented physically as a single hardware module and houses two separate logical devices: a mouse con- troller (logical device 5) and a keyboard controller (logical device 6). the hardware kbc module is integrated to provide the following pin functions: p12, p16, p17, kbrst (p20), ga20 (p21), kbdat, kbclk, mdat and mclk. kbrst and ga20 are implemented as bi-directional, open-drain pins. the keyboard and mouse interfaces are implemented as bi-directional, open-drain pins. their internal connections are shown in figure 5. p10, p11, p13-p15, p22-p27 of the kbc core are not available on dedicated pins; neither are t0 and t1. p10, p11, p22, p23, p26, p27, t0 and t1 are used to implement the keyboard and mouse interface. internal pull-ups are implemented only on p12, p16 and p17. the kbc executes a program fetched from an on-chip 2kbyte rom. the code programmed in this rom is user-customiz- able. the kbc has two interrupt request signals: one for the keyboard and one for the mouse. the interrupt requests are implemented using ports p24 and p25 of the kbc core. the interrupt requests are controlled exclusively by the kbc firm- ware, except for the type and number, which are affected by configuration registers (see section 2.14.2 25). the interrupt requests are implemented as bi-directional signals. when an i/o port is read, all unused bits return the value latched in the output registers of the ports. for kbc firmware that implements interrupt-on-obf schemes, it is recommended to implement it as follows: 1. put the data in dbbout. 2. set the appropriate port bit to issue an interrupt request. figure 5. keyboard and mouse interfaces kbd irq mouse irq kbc kbclk kbdat t0 p10 mclk mdat t1 p11 p26 p27 p23 p22 status dbbin dbbout matrix p24 p25 p20 p21 p12 internal interface bus kbrst ga20 p12 p17 p17 p16 p16
2.0 device architecture and configuration (continued) 65 www.national.com 2.14.2 logical devices 5 and 6 (mouse and keyboard) configuration tables 25 and 26 list the configuration registers that affect the mouse and the keyboard, respectively. only the last register (f0h) is described here. see sections 2.2.3 and 2.2.4 for descriptions of the others. table 25. mouse con?guration registers table 26. keyboard con?guration registers index mouse con?guration register or action type reset 30h activate. see also bit 0 o f the siocf1. when the mouse of the kbc is inactive, the irq selected by the mouse interrupt number and wake-up on irq enable register (index 70h) is not asserted. this register has no effect on host kbc commands handling the ps/2 mouse. r/w 00h 70h mouse interrupt number and wake-up on irq enable register (see note, p. 37). r/w 0ch 71h mouse interrupt type. bits 1,0 are read/write; other bits are read only. r/w 02h 74h report n o dma assignment ro 04h 75h report n o dma assignment ro 04h index keyboard con?guration register or action type reset 30h activate. see also bit 0 o f the siocf1. r/w 01h 60h base address msb register. bits 7-3 (for a15-11) are read only, 00000b. r/w 00h 61h base address lsb register. bits 2-0 are read only 000b. r/w 60h 62h command base address msb register. bits 7-3 (for a15-11) are read only, 00000b. r/w 00h 63h command base address lsb. bits 2-0 are read only 100b. r/w 64h 70h kbd interrupt number and wake-up on irq enable register (see note, p. 37). r/w 01h 71h kbd interrupt type. bits 1,0 are read/write; others are read only. r/w 02h 74h report n o dma assignment. ro 04h 75h report n o dma assignment. ro 04h f0h kbc con?guration register. r/w 40h
2.0 device architecture and configuration (continued) 66 www.national.com 2.14.3 kbc configuration register this register is reset by hardware to 40h. location: index f0h type: r/w usage hints: to change the clock frequency of the kbc: 1. disable the kbc logical devices. 2. change the frequency setting. 3. enable the kbc logical devices. bit 76543210 name kbc clock source reserved tri-state control reset 01000000 required 0 bit description 7-6 kbc clock source. the clock source can be changed only when the kbc is inactive (disabled). bits 7 6 source 0 0 8 mhz 0 1 12 mhz (default) 1 0 16 mhz 1 1 reserved 5-1 reserved. 0 tri-state control. if kbd is inactive (disabled) when this bit is set, the kbd pins (kbclk and kbdat) are in tri- state. if mouse is inactive (disabled) when this bit is set, the mouse pins (mclk and mdat) are in tri-state. 0: disabled (default) 1: enabled
2.0 device architecture and configuration (continued) 67 www.national.com 2.15 general-purpose input/output (gpio) ports configuration 2.15.1 general description the gpio functional block includes 29 pins, arranged in three 8-bit ports (ports 0, 1 and 2) and one 5-bit port (port 3). all pins in port 0 are i/o and have full event detection capability, enabling them to trigger the assertion of irq, smi and pwureq signals. with the exception of bit 5, which is output only, port 1 pins are also i/o with full event detection capability. pins in ports 2 and 3 are i/o but none of them has event detection capability. the 16 runtime registers associated with the five ports are arranged in the gpio address space as shown in table 27. the gpio base address is 16-byte aligned. ad- dress bits 3-0 are used to indicate the register offset. table 27. runtime registers in gpio address space 2.15.2 implementation the standard gpio port with event detection capability (such as ports 0, 1 and 4) has four runtime registers. each pin is associated with a gpio pin configuration register that includes seven configuration bits. ports 2 and 3 are non-standard ports that do not support event detection and therefore differ from the generic model as follows: l they each have two runtime registers for basic functionality: gpdo2/3 and gpdi2/3. event detection registers gpeven2/3 and gpevst2/3 are not available. l only bits 3-0 are implemented in the gpio pin con?guration registers of ports 2 and 3. bits 6-4, associated with the event detection functionality, are reserved. offset mnemonic register name port type 00h gpdo0 gpio data out 0 0 r/w 01h gpdi0 gpio data in 0 ro 02h gpeven0 gpio event enable 0 r/w 03h gpevst0 gpio event status 0 r/w1c 04h gpdo1 gpio data out 1 1 r/w 05h gpdi1 gpio data in 1 ro 06h gpeven1 gpio event enable 1 r/w 07h gpevst1 gpio event status 1 r/w1c 08h gpdo2 data out 2 2 r/w 09h gpdi2 data in 2 ro 0ah gpdo3 data out 3 3 r/w 0bh gpdi3 data in 3 ro
2.0 device architecture and configuration (continued) 68 www.national.com 2.15.3 logical device 7 (gpio) configuration table 28 lists the configuration registers that affect the gpio. only the last three registers (f0h - f2h) are described here. see sections 2.2.3 and 2.2.4 for a detailed description of the others. table 28. gpio con?guration register figure 6 shows the organization of these registers. figure 6. organization of gpio pin registers index con?guration register or action type reset 30h activate. see also bit 7 o f the siocf1 register. r/w 00h 60h base address msb register. r/w 00h 61h base address lsb register. bits 3-0 (for a3-0) are read only, 0000b. r/w 00h 70h interrupt number (see note, p. 37). r/w 00h 71h interrupt type. bit 1 i s read/write. other bits are read only. r/w 03h 74h report n o dma assignment. ro 04h 75h report n o dma assignment. ro 04h f0h gpio pin select register. r/w 00h f1h gpio pin con?guration register. r/w 00h f2h gpio pin event routing register. r/w 00h gpio pin con?guration register pin select port select port 0, pin 0 gpio pin select register gpio pin event routing register port 0, pin 7 port 0 port 3 pin 0 pin 7 port 1, pin 0 port 2, pin 0 port 3, pin 0 port 0 pin 0 pin 7 port 1 port 0, pin 0 port 1, pin 0 port 0, pin 7 con?guration registers (index f0h) (index f1h) (index f2h) event routing registers
2.0 device architecture and configuration (continued) 69 www.national.com 2.15.4 gpio pin select register this register selects the gpio pin (port number and bit number) to be configured (i.e., which register is accessed via the gpio pin configuration register). it is reset by hardware to 00h. location: index f0h type: r/w bit 76543210 name reserved port select reserved pin select reset 00000000 bit description 7 reserved. 6-4 port select. these bits select the gpio port to be configured: 000: port 0 (default) 001, 010, 011: binary value of port numbers 1-3, respectively. all other values are reserved. 3 reserved. 2-0 pin select. these bits select the gpio pin to be con?gured in the selected port: 000, 001, ... 111: binary value of the pin number, 0 , 1 , ... 7 respectively (default=0)
2.0 device architecture and configuration (continued) 70 www.national.com 2.15.5 gpio pin configuration register this register reflects, for both read and write, the register currently selected by the gpio pin select register. all the gpio pin registers that are accessed via this register have a common bit structure, as shown below. this register is reset by hard- ware to 44h, except for ports 2 and 3, which are reset to 04h. location: index f1h type: r/w ports: 0 and 1 (with event detection capability) ports 2 and 3 (without event detection capability) bit 76543210 name reserved event debounce enable event polarity event type lock pull-up control output type output enable reset 01000100 bit 76543210 name reserved lock pull-up control output type output enable reset 00000100 bit description 7 reserved. 6 event debounce enable. (ports 0 and 1 with event detection capability). enables transferring the signal only after a predetermined debouncing period of time. 0: disabled 1: enabled (default) reserved. (ports 2 and 3.) always 0 . 5 event polarity. (ports 0 and 1 with event detection capability). this bit de?nes the polarity of the signal that issues an interrupt from the corresponding gpio pin (falling/low o r rising/high). 0: falling edge or low-level input (default) 1: rising edge or high-level input reserved. (ports 2 and 3.) always 0 . 4 event type. (ports 0 and 1 with event detection capability). this bit de?nes the type of the signal that issues an interrupt from the corresponding gpio pin (edge or level). 0: edge input (default) 1: level input reserved. (ports 2 and 3.) always 0 . 3 lock. this bit locks the corresponding gpio pin. once this bit is set to 1 by software, i t can only be cleared to 0 by system reset or power-off. pin multiplexing is functional until the multiplexing lock bit is 1 (bit 7 o f superi/o con?guration 3 register, siocf3). 0: no effect (default) 1: direction, output type, pull-up and output value locked 2 pull-up control. this bit is used to enable/disable the internal pull-up capability of the corresponding gpio pin. it supports internal pull-ups for the open-drain output buffer type. 0: disabled 1: enabled (default) 1 output type. this bit controls the output buffer type (open-drain or push-pull) of the corresponding gpio pin. 0: open-drain (default) 1: push-pull 0 output enable. this bit indicates the gpio pin output state. i t has no effect on the input path. 0: tri-state (default) 1: output enabled
2.0 device architecture and configuration (continued) 71 www.national.com 2.15.6 gpio event routing register this register enables the routing of the gpio event to irq, smi and/or pwureq signals. it is implemented only for ports 0,1 and 4, which have event detection capability. this register is reset by hardware to 00h. location: index f2h type: r/w bit 76543210 name reserved enable pwureq routing enable smi routing enable irq routing reset 00000001 bit description 7-3 reserved. 2 enable pwureq routing. 0: disabled (default) 1: enabled 1 enable smi routing. 0: disabled (default) 1: enabled 0 enable irq routing. 0: disabled 1: enabled (default)
2.0 device architecture and configuration (continued) 72 www.national.com 2.16 access.bus interface (acb) configuration 2.16.1 general description the acb is a two-wire synchronous serial interface compatible with the access.bus physical layer. the acb uses a 2 4 mhz internal clock. the six runtime registers are shown below. table 29. acb runtime registers 2.16.2 logical device 8 (acb) configuration table 30 lists the configuration registers that affect the acb. only the last register (f0h) is described here. see sections 2.2.3 and 2.2.4 for a detailed description of the others. table 30. acb con?guration registers offset mnemonic register name type 00h acbsda acb serial data r/w 01h acbst acb status varies per bit 02h acbcst acb control status varies per bit 03h acbctl1 acb control 1 r/w 04h acbaddr acb own address r/w 05h acbctl2 acb control 2 r/w index con?guration register or action type reset 30h activate. see also bit 0 o f the siocf1 register. r/w 00h 60h base address msb register. r/w 00h 61h base address lsb register. bits 2-0 (for a2-0) are read only, 000b. r/w 00h 70h interrupt number and wake-up on irq enable register (see note, p. 37). r/w 00h 71h interrupt type. bit 1 i s read/write. other bits are read only. r/w 03h 74h report n o dma assignment. ro 04h 75h report n o dma assignment. ro 04h f0h acb con?guration register. r/w 00h
2.0 device architecture and configuration (continued) 73 www.national.com 2.16.3 acb configuration register this register is reset by hardware to 00h. location: index f0h type: r/w bit 76543210 name reserved internal pull-up enable reserved reset 00000000 bit description 7-3 reserved. 2 internal pull-up enable. 0: no internal pull-up resistors on scl and sda (default) 1: internal pull-up resistors on scl and sda 1-0 reserved.
2.0 device architecture and configuration (continued) 74 www.national.com 2.17 fan speed control and monitor (fscm) configuration 2.17.1 general description this module includes three fan speed control units and three fan speed monitor units. the 15 runtime registers of the six functional blocks are arranged in the address space shown in table 31. the base address is 16-byte aligned. address bits 0-3 are used to indicate the register offset. table 31. runtime registers in fscm address space 2.17.2 logical device 9 (fscm) configuration table 32 lists the configuration registers that affect the fan speed controls and the fan speed monitors. only the last one (f0h) is described here. see sections 2.2.3 and 2.2.4 for a detailed description of the others. table 32. fscm con?guration registers offset mnemonic register name function 00h fcpsr0 fan control 0 pre-scale fan speed control 0 01h fcdcr0 fan control 0 duty cycle 02h fcpsr1 fan control 1 pre-scale fan speed control 1 03h fcdcr1 fan control 1 duty cycle 04h fcpsr2 fan control 2 pre-scale fan speed control 2 05h fcdcr2 fan control 2 duty cycle 06h fmthr0 fan monitor 0 threshold fan speed monitor 0 07h fmspr0 fan monitor 0 speed 08h fmcsr0 fan monitor 0 control & status 09h fmthr1 fan monitor 1 threshold fan speed monitor 1 0ah fmspr1 fan monitor 1 speed 0bh fmcsr1 fan monitor 1 control & status 0ch fmthr2 fan monitor 2 threshold fan speed monitor 2 0dh fmspr2 fan monitor 2 speed 0eh fmcsr2 fan monitor 2 control & status 0fh reserved index con?guration register or action type reset 30h activate. see also bit 0 o f the siocf1 register. r/w 00h 60h base address msb register. r/w 00h 61h base address lsb register. bit 3-0 (for a3-0) are read only, 0000b. r/w 00h 70h interrupt number and wake-up on irq enable register (see note, p. 37). r/w 00h 71h interrupt type. bit 1 i s read/write. other bits are read only. r/w 03h 74h report n o dma assignment. ro 04h 75h report n o dma assignment. ro 04h f0h fan speed control and monitor con?guration 1 register. r/w 00h f1h fan speed control and monitor con?guration 2 register r/w 00h f2h fan speed control ots con?guration register r/w 00h
2.0 device architecture and configuration (continued) 75 www.national.com 2.17.3 fan speed control and monitor configuration 1 register this register is reset by hardware to 00h. location: index f0h type: r/w bit 76543210 name fan speed invert 1 enable fan speed control 1 enable fan speed monitor 1 enable fan speed invert 0 enable fan speed control 0 enable fan speed monitor 0 enable reserved tri-state control reset 00000000 bit description 7 fan speed invert 1 enable. 0: disabled (default) 1: enabled 6 fan speed control 1 enable. 0: disabled (default) 1: enabled 5 fan speed monitor 1 enable. 0: disabled (default) 1: enabled 4 fan speed invert 0 enable. 0: disabled (default) 1: enabled 3 fan speed control 0 enable. 0: disabled (default) 1: enabled 2 fan speed monitor 0 enable. 0: disabled (default) 1: enabled 1 reserved. 0 tri-state control. when enabled and the device is inactive, the logical device output pins are in tri-state. 0: disabled (default) 1: enabled
2.0 device architecture and configuration (continued) 76 www.national.com 2.17.4 fan speed control and monitor configuration 2 register this register is reset by hardware to 00h. location: index f1h type: r/w 2.17.5 fan speed control ots configuration register (fcocr) location: index f2h type: r/w bit 76543210 name reserved fan speed invert 2 enable fan speed control 2 enable fan speed monitor 2 enable reset 00000000 bit description 7-3 reserved. 2 fan speed invert 2 enable. 0: disabled (default) 1: enabled 1 fan speed control 2 enable. 0: disabled (default) 1: enabled 0 fan speed monitor 2 enable. 0: disabled (default) 1: enabled bit 76543210 name reserved fan 2 enable on ots fan 1 enable on ots fan 0 enable on ots reset 00000000 bit description 7-3 reserved. 2 fan 2 enable on ots. enables fan 2 at 100% duty cycle when an ots event becomes active. 0: fan 2 operates as de?ned by the pwm mechanism 1: fan 2 is forced to 100% duty cycle when the ots output form any o f the temperature measurement channels (tms or vlm) becomes active. 1 fan 1 enable on ots. enables fan 1 at 100% duty cycle when an ots event becomes active. 0: fan 1 operates as de?ned by the pwm mechanism 1: fan 1 is forced to 100% duty cycle when the ots output form any o f the temperature measurement channels (tms or vlm) becomes active. 0 fan 0 enable on ots. enables fan 0 at 100% duty cycle when an ots event becomes active. 0: fan 0 operates as de?ned by the pwm mechanism 1: fan 0 is forced to 100% duty cycle when the ots output form any o f the temperature measurement channels (tms or vlm) becomes active.
2.0 device architecture and configuration (continued) 77 www.national.com 2.18 watchdog timer (wdt) configuration 2.18.1 logical device 10 (wdt) configuration table 33 lists the configuration registers that affect the watchdog timer. only the last register (f0h) is described here. see sections 2.2.3 and 2.2.4 for a detailed description of the others. table 33. wdt con?guration registers 2.18.2 watchdog timer configuration register this register is reset by hardware to 02h. location: index f0h type: r/w index con?guration register or action type reset 30h activate. when bit 0 i s cleared, the registers of this logical device are not accessible. r/w 00h 60h base address msb register. r/w 00h 61h base address lsb register. bits 1 and 0 ( for a 1 and a0) are read only, 00b. r/w 00h 70h interrupt number (for routing the wdo signal) and wake-up on irq enable register (see note, p. 37). r/w 00h 71h interrupt type. bit 1 i s read/write. other bits are read only. r/w 03h 74h report n o dma assignment. ro 04h 75h report n o dma assignment. ro 04h f0h watchdog timer con?guration register. r/w 02h bit 76543210 name reserved output type internal pull-up enable power mode control tri-state control reset 00000010 bit description 7-4 reserved. 3 output type. this bit controls the buffer type (open-drain or push-pull) of the wdo pin. 0: open-drain (default) 1: push-pull 2 internal pull-up enable. this bit controls the internal pull-up resistor on the wdo pin. 0: disabled (default) 1: enabled 1 power mode control. 0: low p ower mode: watchdog timer clock disabled. wdo output signal is set to 1. registers are accessible and maintained (unlike active bit in index 30h that also prevents access to watchdog timer registers). 1: normal power mode: watchdog timer clock enabled. watchdog timer is functional when the logical device is active (default). 0 tri-state control. when enabled and the device is inactive, the logical device output pins are in tri-state. 0: disabled (default) 1: enabled
2.0 device architecture and configuration (continued) 78 www.national.com 2.19 game port (gmp) configuration 2.19.1 logical device 11 (gmp) configuration table 34 lists the configuration registers that affect the game port. only the last register (f0h) is described here. see sec- tions 2.2.3 and 2.2.4 for a detailed description of the others. table 34. gmp con?guration registers 2.19.2 game port configuration register this register is reset by hardware to 00h. location: index f0h type: r/w usage hint: to operate gmp enhanced features, make sure to locate its base address within the lpc wide generic address range. index con?guration register or action type reset 30h activate. when bit 0 i s cleared, the registers of this logical device are not accessible. r/w 00h 60h base address msb register r/w 02h 61h base address lsb register. bits 3-0 (for a3-a0) are read only, 0000b. r/w 00h 70h interrupt number and wake-up on irq enable register. r/w 00h 71h interrupt type. bit 1 i s read/write. other bits are read only. r/w 03h 74h report n o dma assignment ro 04h 75h report n o dma assignment ro 04h f0h game port con?guration register r/w 00h bit 76543210 name reserved internal pull-up enable reserved reset 00000000 bit description 7-3 reserved. 2 internal pull-up enable. when the gmp functions are selected, this bit controls the internal pull-up resistor on pins 119 (gpio22/joyabtn0), 120 (gpio23/joyabtn1), 123 (gpio26/joybbtn0) and 124 (gpio27/joybbtn1). 0: disabled (default) 1: enabled 1-0 reserved.
2.0 device architecture and configuration (continued) 79 www.national.com 2.20 midi port (midi) configuration 2.20.1 logical device 12 (midi) configuration table 34 lists the configuration registers that affect the midi port. only the last register (f0h) is described here. see sections 2.2.3 and 2.2.4 for a detailed description of the others. table 35. midi con?guration registers 2.20.2 midi port configuration register this register is reset by hardware to 00h. location: index f0h type: r/w usage hint: to operate midi enhanced features, make sure to locate its base address within the lpc wide generic address range. index con?guration register or action type reset 30h activate. when bit 0 i s cleared, the registers of this logical device are not accessible. r/w 00h 60h base address msb register r/w 03h 61h base address lsb register bits 1-0 (for a1-a0) are read only, 00b. r/w 30h 70h interrupt number and wake-up on irq enable. r/w 00h 71h interrupt type. bit 1 i s read/write. other bits are read only. r/w 03h 74h report n o dma assignment ro 04h 75h report n o dma assignment ro 04h f0h midi port con?guration register r/w 00h bit 76543210 name reserved internal pull-up enable reserved tri-state control reset 00000000 bit description 7-3 reserved. 2 internal pull-up enable. this bit controls the internal pull-up resistor on pin 126 (gpio31/mdrx). 0: disabled (default) 1: enabled 1 reserved. 0 tri-state control. when enabled and the device is inactive, the logical device output pins are in tri-state. 0: disabled (default) 1: enabled
2.0 device architecture and configuration (continued) 80 www.national.com 2.21 voltage level monitor (vlm) configuration 2.21.1 logical device 13 (vlm) configuration table 36 lists the configuration registers that affect the vlm. see sections 2.2.3 and 2.2.4 for a detailed description of these registers. table 36. vlm con?guration registers 2.22 temperature sensor (tms) configuration 2.22.1 logical device 14 (tms) configuration table 37 lists the configuration registers that affect the tms. see sections 2.2.3 and 2.2.4 for a detailed description of these registers.the ots, alert, irq and smi signals are routed through the configuration module. ots is routed to a pin, irq and smi are routed to a designated interrupt signal and alert is not connected. when measuring temperature using ther- mistors that are connected to the vlm module, the ots, alert, smi and irq signals are routed through the tms config- uration. therefore, ensure that you set the tms configuration registers (described in table 37) and enable the tms module whenever temperature measurement is in use. in the tms or vlm module, enable the required source of irq, smi and ots signals via the configuration registers inside the module. table 37. tms con?guration registers index con?guration register or action type reset 30h activate. when bit 0 i s cleared, the registers of this logical device are not accessible. r/w 00h 60h base address msb register r/w 00h 61h base address lsb register. bits 3-0 (for a3-0) are read only, 0000b. r/w 00h 70h interrupt number r/w 00h 71h interrupt type. bit 1 i s read/write. other bits are read only. r/w 03h 74h report n o dma assignment ro 04h 75h report n o dma assignment ro 04h index con?guration register or action type reset 30h activate. when bit 0 i s cleared, the registers of this logical device are not accessible. r/w 00h 60h base address msb register r/w 00h 61h base address lsb register. bits 3-0 (for a3-0) are read only, 0000b. r/w 00h 70h interrupt number r/w 00h 71h interrupt type. bit 1 i s read/write. other bits are read only. r/w 03h 74h report n o dma assignment ro 04h 75h report n o dma assignment ro 04h
81 www.national.com 3.0 system wake-up control (swc) 3.1 overview the swc recognizes the following maskable system events: l modem ring ( ri1 and ri2 pins). l telephone ring ( ring input pin). l keyboard activity or speci?c programmable key sequence. l mouse activity or speci?c programmable sequence of clicks and movements. l programmable consumer electronics ir (ceir) address. l wake-up on module irqs for fdc, parallel port, serial ports 1 and 2, mouse, kbc, acb, fan speed control and monitor (fscm) and watchdog timer (wdt), game port and midi port. l eight v sb -powered, general-purpose input events (via gpioe0-5 and gpie6-7). l 15 v dd -powered, gpio-triggered events (via gpio00-07, gpio10-14, gpio16-17). l software event. the swc notifies the device when any of these events occur by asserting one or more of the following output pins: l power-up request ( pwureq). l system management interrupt ( smi). l interrupt request (via serirq). l power button ( pwbt out). figure 7 shows the block diagram of the swc. figure 7. swc block diagram filters and polarity selection logic wake-up mode control (extension) logic wake-up event detection and routing logic wake-up event sources irq smi pwureq 16 16 16 100 msec pulse generator 14 internal crowbar pwbtin power-supplies system acpi (v dd , v sb ) status state indication pwbtout wake-up extension enable registers wake-up configuration and control registers acpi enable, status and routing control registers 16 msec debouncer
3.0 system wake-up control (swc) (continued) 82 www.national.com in addition to the event detection and system notification capabilities, the swc operates several general-purpose i/o pins powered by v sb . these pins can be used to perform various tasks while v sb is present and v dd is not. 3.2 functional description the swc monitors 16 system events or activities. upon entering the swc, the events pass through a filter (where applica- ble) and polarity adjustment logic. after filtering and polarity adjustment, each event enters the wake-up mode control (ex- tension) logic, which determines its effect during the various system power states. the wake-up mode control (extension) logic also controls the effect of each wake-up event on the power button output ( pwbtout). see figure 7 for an illustration of this mechanism. after the wake-up mode is determined for all events, each one of them is fed into a dedicated detector that determines when this event is active, according to predetermined (either fixed or programmable) criteria. a set of dedicated registers is used to determine the wake-up criteria, including the ceir address and the keyboard sequence. two wake-up events status registers (wk_stsn) hold a status bit for each of the 16 events. six wake-up events routing control registers (wk_enn wk_smienn and wk_irqenn) hold three routing enable bits for each of the 16 events to allow selective routing of these events to pwureq, smi and/or the assigned swc interrupt request (irq) channel. upon detection of any active event, the corresponding status bit is set to 1 regardless of any routing enable bit. if both the status bit and a routing enable bit corresponding to a specific event are set to 1 (no matter in what order), the output pin corresponding to that routing enable bit is asserted. the status bit is de-asserted by writing 1 t o it. writing 0 t o a routing enable bit of an event prevents it from issuing the corresponding system notification but does not affect the status bit. figure 8 show the routing scheme of detected wake-up events to the various means of system notification. figure 8. wake-up events routing scheme to enable the assertion of smi by detected wake-up events, it is necessary to either select the smi function on a device pin or route it to an interrupt request channel via the devices configuration registers. event i detection wk_smienn.i wk_irqenn.i wk_enn.i wake-up event i from wake-up pwureq smi irq event routing logic wk_stsn.i extension logic
3.0 system wake-up control (swc) (continued) 83 www.national.com six wake-up extension enable registers (wk_x1en0,1 wk_x2en0,1 and wk_x3en0,1) hold three configuration bits for each of the 16 events to allow selective routing of detected events to the power button ( pwbtout) pulse generator and to control the wake-up mode for each one of them. figure 9 illustrates the wake-up mode control (extension) mechanism. figure 9. wake-up mode control (extension) mechanism to operate the power button pulse generator, the psldc0,1 straps must be set to enable the power supply control function (see section 2.6). in addition, one of the following conditions must be satisfied: l slps5 is active (the system is in sleep state 5), or l legacy power button is enabled, or l power button operation in sleep state 3 i s enabled. the two latter conditions are determined by device configuration registers. (refer to the device architecture and configura- tion chapter.) in addition to monitoring various system events, the swc operates several general-purpose i/o (gpio) pins powered by v sb . four runtime data registers (sb_gpdon and sb_gpdin) hold a data out bit and a data in bit for each v sb -powered gpio pin. in addition, each gpio pin has a dedicated configuration register that controls its characteristics. these configu- ration registers are accessed via a set of standby gpio pin select and pin configuration registers (sbgpsel and sbg- pcfg). for a detailed description of the v sb powered gpio pins, see section 3.4.30. the swc logic is powered by v sb . the swc control and configuration registers are battery backed, powered by v pp . the setup of the wake-up events, including programmable sequences, is retained throughout power failures (no v sb ) a s long as the battery is connected. v pp is taken from v sb if v sb is greater than the minimum (min) value defined in the device char- acteristics chapter; otherwise, v bat is used as the v pp source. hardware reset does not affect these registers. they are reset only by software reset or power-up of v pp . 3.3 event detection 3.3.1 modem ring high-to-low transitions on ri1 or ri2 indicate the detection of a ring in an external modem connected to serial port 1 o r serial port 2, respectively, and can be used as wake-up events. 3.3.2 telephone ring a telephone ring is detected by the swc by processing the raw signal coming directly from the telephone line into the ring input pin. detection of a pulse-train with a frequency higher than 16 hz lasting at least 0.19 sec is used as a wake-up event. the ring pulse-train detection is achieved by monitoring the falling edges on ring in time slots of 62.5 msec (a 16 hz cycle). a positive detection occurs if falling edges of ring are detected in three consecutive time slots, following a time slot in which no ring falling edge is detected. this detection method guarantees the detection of a ring pulse-train with fre- quencies higher than 16 hz. it ?lters out (does not detect) pulses of less than 10 hz and may detect pulses between 10 hz to 16 hz. wk_x2enn.i wk_x1enn.i wake-up raw event i v dd present post v dd power-on silence to event i detection logic wk_x3enn.i to power button pulse generator post v sb power-on silence enable power button pulse
3.0 system wake-up control (swc) (continued) 84 www.national.com 3.3.3 keyboard and mouse activity the detection of either any activity or a specific predetermined keyboard or mouse activity can be used as a wake-up event. the keyboard wake-up detection can be programmed to detect: l any keystroke. l a speci?c programmable sequence of up to eight alphanumeric keystrokes. l any programmable sequence of up to 8 bytes of data received from the keyboard. the mouse wake-up detection can be programmed to detect either a mouse click or movement, a specific programmable click (left or right) or double-clicks. the keyboard or mouse event detection operates independently of the kbc (which is powered down with the rest of the system). 3.3.4 ceir address a ceir transmission received on an irrx pin in a pre-selected standard (nec, rca or rc-5) is matched against a pro- grammable ceir address. detection of a match can be used as a wake-up event. whenever an ir signal is detected, the receiver immediately enters the active state. when this happens, the receiver keeps sampling the ir input signal and generates a bit string where a logic 1 indicates an idle condition and a logic 0 indicates the presence of ir energy. the received bit string is de-serialized and assembled into 8-bit characters. the expected ceir protocol of the received signal should be configured through bits 5,4 at the ceir wake-up control reg- ister (see section 3.4.22). the ceir wake-up address register (irwad) holds the unique address to be compared with the address contained in the incoming ceir message. if ceir is enabled (bit 0 o f the irwcr register is 1) and an address match occurs, then the ceir event status bit of the wk_sts0 register is set to 1 (see section 3.4.2). the ceir address shift register holds the received address, which is compared with the address contained in the irwad. the comparison is affected also by the ceir wake-up address mask register (irwam) in which each bit determines wheth- er to ignore the corresponding bit in the irwad. if ceir routing to interrupt request is enabled, the assigned swc interrupt request may be used to indicate that a complete address has been received. to get this interrupt when the address is completely received, the irwam should be written with ffh. once the interrupt is received, the value of the address can be read from the adsr register. another parameter used to determine whether a ceir signal is to be considered valid is the bit cell time width. there are four time ranges for the different protocols and carrier frequencies. four pairs of registers define the low and high limits of each time range. (see sections 3.4.29 through for more details regarding the recommended values for each protocol.) the ceir address detection operates independently of the serial port with the ir (which is powered down with the rest of the system). 3.3.5 standby general-purpose input events a general-purpose event is defined as the detection of falling edge or rising edge on a specific signal. each signals event is configurable via software. gpioe0-5 and gpie6-7 may t rigger a system notification by any o f the means mentioned in section 3.1. a debouncer of 16 ms is enabled (default) on each event. it may be disabled by software. 3.3.6 gpio-triggered events a gpio-triggered event is defined as the detection of falling edge or rising edge on a specific gpio signal whose status bit is routed to pwureq. each signals event is configurable via software in the gpio logical device configuration registers. gpio00-07, gpio10-14, gpio16-17 may t rigger a system noti?cation only by pwureq. other means of system noti?cation triggered by gpios are available via the gpio logical device con?guration registers. a debouncer of 16 ms is enabled (default) on each event. it may be disabled by software. all gpio pins are powered by v dd and therefore can cause an assertion of pwureq only when v dd is present. 3.3.7 software event a software event is defined as writing 1 t o the software event status bit of the wk_sts0 register. once this bit is set to 1, it has the same effect as any other event status bit. since wk_sts0 is accessible only when v dd is present, the software event can be activated only when v dd is present. 3.3.8 module irq wake-up event a module irq wake-up event is defined as the leading edge of the irq assertion of any of the following logical devices: fdc, parallel port, serial ports 1 and 2, mouse, kbc, acb, fan speed control and monitor (fscm), game port and midi port.
3.0 system wake-up control (swc) (continued) 85 www.national.com to enable the irq of a specific logical device to trigger a wake-up event, the associated enable bit must be set to 1. this is bit 4 o f the interrupt number and wake-up on irq enable register, located at index 70h in the configuration space of the logical device (see table 10 in device architecture and configuration chapter). when this bit is set, any irq assertion of the corresponding logical device activates the module irq wake-up event. therefore, the module irq wake-up event is a com- bination of all irq signals of the logical devices for which wake-up on irq is enabled. note that index 70h has two functions: it is used to set irq and to enable wake-up on irq. if the bios routine that sets irq does not use a read-modify-write sequence, it might reset bit 4, which is the wake-up on irq bit. to ensure that the system wakes up, the bios must set bit 4 before the system goes to sleep. when the event is detected as active, its associated status bit (bit 7 o f the wk0_sts register) is set to 1. if the associated enable bit (bit 7 o f the wk_en0 register) is also set to 1, the pwureq output is asserted. it remains asserted until the status bit is cleared. since all the logical devices listed above are powered by v dd , a module irq event can be activated only when v dd is present. 3.4 swc registers the swc registers are organized in four banks, all of which are battery-backed. the offsets are related to a base address that is determined by the swc base address register in the device configuration registers. the lower 19 offsets are common to the four banks, while the upper offsets (13-1fh) are divided as follows: l bank 0 holds the keyboard/mouse control registers. l bank 1 holds the ceir control registers. l bank 2 holds the event routing con?guration and wake-up extension control registers. l bank 3 holds the standby general-purpose i/o (gpio) pins con?guration registers. the active bank is selected through the configuration bank select field (bits 1-0) in the wake-up configuration register (wk_cfg). see section 3.4.6. as a programming aid, the registers are described in this chapter according to the following functional groupings: l general status, enable, con?guration and routing registers. l extension enable registers. l ps/2 event con?guration registers. l ceir event con?guration registers. l standby gpio con?guration and control registers. the following abbreviations are used to indicate the register type: l r/w = read/write. l r = read from a speci?c address returns the value of a speci?c register. w rite to the same address is to a different register. l w = w rite. l ro = read only. l r/w1c = read/write 1 t o clear. w riting 1 t o a bit clears it to 0. writing 0 has no effect.
3.0 system wake-up control (swc) (continued) 86 www.national.com 3.4.1 swc register map the following tables list the swc registers. for the swc register bitmap, see section 3.5. table 38. banks 0, 1, 2 and 3 - the common control and status register map table 39. bank 0 - ps/2 keyboard/mouse wake-up con?guration and control register map table 40. bank 1 - ceir wake-up con?guration and control register map offset mnemonic register name type section 00h wk_sts0 wake-up events status 0 r/w1c 3.4.2 01h wk_sts1 wake-up events status 1 r/w1c 3.4.3 02h wk_en0 wake-up enable 0 r/w 3.4.4 03h wk_en1 wake-up enable 1 r/w 3.4.5 04h wk_cfg wake-up con?guration r/w 3.4.6 05h-07h reserved 08h sb_gpdo0 standby gpioe/gpie data out 0 r/w 3.4.33 09h sb_gpdi0 standby gpioe/gpie data in 0 ro 3.4.34 0ah sb_gpdo1 standby gpos data out 1 r/w 3.4.35 0bh sb_gpdi1 standby gpis data in 1 ro 3.4.36 0ch-12h reserved offset mnemonic register name type section 13h ps2ctl ps/2 protocol control r/w 3.4.18 14h-15h reserved 16h kdsr keyboard data shift ro 3.4.19 17h mdsr mouse data shift ro 3.4.20 18h-1fh ps2key0-ps2key7 ps/2 keyboard key data r/w 3.4.21 offset mnemonic register name type section 13h irwcr ceir wake-up control r/w 3.4.22 14h reserved 15h irwad ceir wake-up address r/w 3.4.23 16h irwam ceir wake-up address mask r/w 3.4.24 17h adsr ceir address shift r/o 3.4.25 18h irwtr0l ceir wake-up, range 0, low limit r/w 3.4.26 19h irwtr0h ceir wake-up, range 0, high limit r/w 3.4.26 1ah irwtr1l ceir wake-up, range 1, low limit r/w 3.4.27 1bh irwtr1h ceir wake-up, range 1, high limit r/w 3.4.27 1ch irwtr2l ceir wake-up, range 2, low limit r/w 3.4.28 1dh irwtr2h ceir wake-up, range 2, high limit r/w 3.4.28 1eh irwtr3l ceir wake-up, range 3, low limit r/w 3.4.29 1fh irwtr3h ceir wake-up, range 3, high limit r/w 3.4.29
3.0 system wake-up control (swc) (continued) 87 www.national.com table 41. bank 2 - event routing con?guration register map table 42. bank 3 - standby gpio pin con?guration register map offset mnemonic register name type section 13h wk_smien0 wake-up smi enable 0 r/w 3.4.7 14h wk_smien1 wake-up smi enable 1 r/w 3.4.8 15h wk_irqen0 wake-up interrupt request enable 0 r/w 3.4.9 16h wk_irqen1 wake-up interrupt request enable 1 r/w 3.4.10 17h wk_x1en0 wake-up extension 1 enable 0 r/w 3.4.11 18h wk_x1en1 wake-up extension 1 enable 1 r/w 3.4.12 19h wk_x2en0 wake-up extension 2 enable 0 r/w 3.4.13 1ah wk_x2en1 wake-up extension 2 enable 1 r/w 3.4.14 1bh wk_x3en0 wake-up extension 3 enable 0 r/w 3.4.15 1ch wk_x3en1 wake-up extension 3 enable 1 r/w 3.4.16 1dh-1fh reserved offset mnemonic register name type section 13h sbgpsel standby gpio pin select r/w 3.4.31 14h sbgpcfg standby gpio pin con?guration r/w 3.4.32 15h-1fh reserved
3.0 system wake-up control (swc) (continued) 88 www.national.com 3.4.2 wake-up events status register 0 (wk_sts0) this register is set to 00h on power-up of v pp, v sb or software reset. it indicates which of the corresponding eight wake-up events have occurred. writing 1 t o a bit clears it to 0. writing 0 has no effect. bit 6 o f this register has a special type, a s described in the table below. location: offset 00h type: r/w1c bit 76543210 name module irq event status software event status gpio event status ceir event status mouse event status kbd event status ri2 event status ri1 event status reset 00000000 bit description 7 module irq event status. this sticky bit shows the status of the module irq event detection. 0: event not active (default) 1: event active 6 software event status . w riting 1 t o this bit inverts its value. 0: event not active (default) 1: event active 5 gpio event status. this sticky bit shows the status of the v dd gpio event detection. 0: event not detected (default) 1: event detected 4 ceir event status. 0: event not detected (default) 1: event detected 3 mouse event status . 0: event not detected (default) 1: event detected 2 kbd event status. 0: event not detected (default) 1: event detected 1 ri2 event status. 0: event not detected (default) 1: event detected 0 ri1 event status. 0: event not detected (default) 1: event detected
3.0 system wake-up control (swc) (continued) 89 www.national.com 3.4.3 wake-up events status register (wk_sts1) this register is set to 00h on power-up of v pp, v sb or software reset. it indicates which of the corresponding eight wake-up events have occurred. writing 1 to a bit clears it to 0. writing 0 has no effect. location: offset 01h type: r/w1c bit 76543210 name gpie7 event status gpie6 event status gpie5 event status gpie4/ ring event status gpie3 event status gpie2 event status gpie1 event status gpie0 event status reset 00000000 bit description 7 gpie7 event status. 0: event not detected (default) 1: event detected 6 gpie6 event status. 0: event not detected (default) 1: event detected 5 gpie5 event status. 0: event not detected (default) 1: event detected 4 gpie4/ ring event status. this sticky bit shows the status of either gpie4 or ring event detection, according to the function currently selected on pin 27. 0: event not detected (default) 1: event detected 3 gpie3 event status. 0: event not detected (default) 1: event detected 2 gpie2 event status. 0: event not detected (default) 1: event detected 1 gpie1 event status. 0: event not detected (default) 1: event detected 0 gpie0 event status. 0: event not detected (default) 1: event detected
3.0 system wake-up control (swc) (continued) 90 www.national.com 3.4.4 wake-up events enable register (wk_en0) this register is set to 00h on power-up of v pp or software reset. detected wake-up events that are enabled activate the pwureq signal. location: offset 02h type: r/w bit 76543210 name module irq event enable software event enable gpio event enable ceir event enable mouse event enable kbd event enable ri2 event enable ri1 event enable reset 00000000 bit description 7 module irq event enable. 0: disabled (default) 1: enabled 6 software event enable. 0: disabled (default) 1: enabled 5 gpio event enable. 0: disabled (default) 1: enabled 4 ceir event enable. 0: disabled (default) 1: enabled 3 mouse event enable. 0: disabled (default) 1: enabled 2 kbd event enable. 0: disabled (default) 1: enabled 1 ri2 event enable. 0: disabled (default) 1: enabled 0 ri1 event enable. 0: disabled (default) 1: enabled
3.0 system wake-up control (swc) (continued) 91 www.national.com 3.4.5 wake-up events enable register 1 (wk_en1) this register is set to 00h on power-up of v pp or software reset. detected wake-up events that are enabled activate the pwureq signal. location: offset 03h type: r/w bit 76543210 name gpie7 event enable gpie6 event enable gpie5 event enable gpie4/ ring event enable gpie3 event enable gpie2 event enable gpie1 event enable gpie0 event enable reset 00000000 bit description 7 gpie7 event enable. 0: disabled (default) 1: enabled 6 gpie6 event enable. 0: disabled (default) 1: enabled 5 gpie5 event enable. 0: disabled (default) 1: enabled 4 gpie4/ ring event enable. 0: disabled (default) 1: enabled 3 gpie3 event enable. 0: disabled (default) 1: enabled. 2 gpie2 event enable. 0: disabled (default) 1: enabled 1 gpie1 event enable. 0: disabled (default) 1: enabled 0 gpie0 event enable. 0: disabled (default) 1: enabled
3.0 system wake-up control (swc) (continued) 92 www.national.com 3.4.6 wake-up configuration register (wk_cfg) this register is set to 00h on power-up of v pp or software reset. it enables access to ceir registers, keyboard/mouse reg- isters, event routing control registers or standby gpio registers. location: offset 04h type: r/w bit 76543210 name reserved enable power button pulse on s3 swap kbc inputs con?guration bank select reset 00000000 required 0 0 bit description 7-4 reserved. 3 enable power button pulse on s3. 0: disabled (default) 1: enabled 2 swap kbc inputs. 0: no swapping (default) 1: kbd (kbclk, kbdat) and mouse (mclk, mdat) inputs swapped 1-0 con?guration bank select. bits 1 0 bank register 0 0 0 keyboard/mouse 0 1 1 ceir 1 0 2 e vent routing, wake-up extension 1 1 3 standby gpio
3.0 system wake-up control (swc) (continued) 93 www.national.com 3.4.7 wake-up events routing to smi enable register 0 (wk_smien0) this register is set to 00h on power-up of v pp or software reset. it controls the routing of detected wake-up events to the smi signal. detected wake-up events that are enabled activate the smi signal regardless of the value of the wk_en0 reg- ister. location: bank 2, offset 13h type: r/w bit 76543210 name reserved software event to smi enable reserved ceir event to smi enable mouse event to smi enable kbd event to smi enable ri2 event to smi enable ri1 event to smi enable reset 00000000 bit description 7 reserved. 6 software event to smi enable. 0: disabled (default) 1: enabled 5 reserved. 4 ceir event to smi enable. 0: disabled (default) 1: enabled 3 mouse event to smi enable. 0: disabled (default) 1: enabled 2 kbd event to smi enable. 0: disabled (default) 1: enabled 1 ri2 event to smi enable. 0: disabled (default) 1: enabled 0 ri1 event to smi enable. 0: disabled (default) 1: enabled
3.0 system wake-up control (swc) (continued) 94 www.national.com 3.4.8 wake-up events routing to smi enable register 1 (wk_smien1) this register is set to 00h on power-up of v pp or software reset. it controls the routing of detected wake-up events to the smi signal. detected wake-up events that are enabled activate the smi signal regardless of the value of the wk_en1 reg- ister. location: bank 2, offset 14h type: r/w bit 76543210 name gpie7 event to smi enable gpie6 event to smi enable gpie5 event to smi enable gpie4/ ring event to smi enable gpie3 event to smi enable gpie2 event to smi enable gpie1 event to smi enable gpie0 event to smi enable reset 00000000 bit description 7 gpie7 event to smi enable. 0: disabled (default) 1: enabled 6 gpie6 event to smi enable. 0: disabled (default) 1: enabled 5 gpie5 event to smi enable. 0: disabled (default) 1: enabled 4 gpie4/ ring event to smi enable. 0: disabled (default) 1: enabled 3 gpie3 event to smi enable. 0: disabled (default) 1: enabled. 2 gpie2 event to smi enable. 0: disabled (default) 1: enabled 1 gpie1 event to smi enable. 0: disabled (default) 1: enabled 0 gpie0 event to smi enable. 0: disabled (default) 1: enabled
3.0 system wake-up control (swc) (continued) 95 www.national.com 3.4.9 wake-up events routing to irq enable register 0 (wk_irqen0) this register is set to 00h on power-up of v pp or software reset. it controls the routing of detected wake-up events to the assigned swc interrupt request (irq) channel. detected wake-up events that are enabled activate the assigned irq chan- nel regardless of the value of the wk_en0 register. location: bank 2, offset 15h type: r/w bit 76543210 name reserved software event to irq enable reserved ceir event to irq enable mouse event to irq enable kbd event to irq enable ri2 event to irq enable ri1 event to irq enable reset 00000000 bit description 7 reserved. 6 software event to irq enable. 0: disabled (default) 1: enabled 5 reserved. 4 ceir event to irq enable. 0: disabled (default) 1: enabled 3 mouse event to irq enable. 0: disabled (default) 1: enabled 2 kbd event to irq enable. 0: disabled (default) 1: enabled. 1 ri2 event to irq enable. 0: disabled (default) 1: enabled 0 ri1 event to irq enable. 0: disabled (default) 1: enabled
3.0 system wake-up control (swc) (continued) 96 www.national.com 3.4.10 wake-up events routing to irq enable register 1 (wk_irqen1) this register is set to 00h on power-up of v pp or software reset. it controls the routing of detected wake-up events to the assigned swc irq channel. detected wake-up events that are enabled activate the irq signal regardless of the value of the wk_en1 register. location: bank 2, offset 16h type: r/w bit 76543210 name gpie7 event to irq enable gpie6 event to irq enable gpie5 event to irq enable gpie4/ ring event to irq enable gpie3 event to irq enable gpie2 event to irq enable gpie1 event to irq enable gpie0 event to irq enable reset 00000000 bit description 7 gpie7 event to irq enable. 0: disabled (default) 1: enabled 6 gpie6 event to irq enable. 0: disabled (default) 1: enabled 5 gpioe5 event to irq enable. 0: disabled (default) 1: enabled 4 gpie4/ ring event to irq enable. 0: disabled (default) 1: enabled 3 gpie3 event to irq enable. 0: disabled (default) 1: enabled. 2 gpie2 event to irq enable. 0: disabled (default) 1: enabled 1 gpie1 event to irq enable. 0: disabled (default) 1: enabled 0 gpie0 event to irq enable. 0: disabled (default) 1: enabled
3.0 system wake-up control (swc) (continued) 97 www.national.com 3.4.11 wake-up extension 1 enable register 0 (wk_x1en0) this register is set to 1fh on power-up of v pp or software reset. it controls the routing of raw wake-up events to event de- tectors while v dd is present. wake-up events that are enabled are routed to their event detectors while v dd is present. location: bank 2, offset 17h type: r/w bit 76543210 name reserved ceir event ex. 1 enable mouse event ex. 1 enable kbd event ex. 1 enable ri2 event ex. 1 enable ri1 event ex.1 enable reset 00011111 bit description 7-5 reserved. 4 ceir event extension 1 enable. 0: disabled 1: enabled (default) 3 mouse event extension 1 enable. 0: disabled 1: enabled (default) 2 kbd event extension 1 enable. 0: disabled 1: enabled (default) 1 ri2 event extension 1 enable. 0: disabled 1: enabled (default) 0 ri1 event extension 1 enable. 0: disabled 1: enabled (default)
3.0 system wake-up control (swc) (continued) 98 www.national.com 3.4.12 wake-up extension 1 enable register 1 (wk_x1en1) this register is set to ffh on power-up of v pp or software reset. it controls the routing of raw wake-up events to event de- tectors while v dd is present. wake-up events that are enabled are routed to their event detectors while v dd is present. location: bank 2, offset 18h type: r/w bit 76543210 name gpie7 event ex. 1 enable gpie6 event ex. 1 enable gpie5 event ex. 1 enable gpie4/ ring event ex. 1 enable gpie3 event ex. 1 enable gpie2 event ex. 1 enable gpie1 event ex. 1 enable gpie0 event ex. 1 enable reset 11111111 bit description 7 gpie7 event extension 1 enable. 0: disabled 1: enabled (default) 6 gpie6 event extension 1 enable. 0: disabled 1: enabled (default) 5 gpie5 event extension 1 enable. 0: disabled 1: enabled (default) 4 gpie4/ ring event extension 1 enable. 0: disabled 1: enabled (default) 3 gpie3 event extension 1 enable. 0: disabled 1: enabled (default) 2 gpie2 event extension 1 enable. 0: disabled 1: enabled (default) 1 gpie1 event extension 1 enable. 0: disabled 1: enabled (default) 0 gpie0 event extension 1 enable. 0: disabled 1: enabled (default)
3.0 system wake-up control (swc) (continued) 99 www.national.com 3.4.13 wake-up extension 2 enable register 0 (wk_x2en0) this register is set to 1fh on power-up of v pp or software reset. it controls the routing of raw wake-up events to event de- tectors while v dd is not present. wake-up events that are enabled are routed to their event detectors while v dd is not present. location: bank 2, offset 19h type: r/w bit 76543210 name reserved ceir event ex. 2 enable mouse event ex. 2 enable kbd event ex. 2 enable ri2 event ex. 2 enable ri1 event ex. 2 enable reset 00011111 bit description 7-5 reserved. 4 ceir event extension 2 enable. 0: disabled 1: enabled (default) 3 mouse event extension 2 enable. 0: disabled 1: enabled (default) 2 kbd event extension 2 enable. 0: disabled 1: enabled (default) 1 ri2 event extension 2 enable. 0: disabled 1: enabled (default) 0 ri1 event extension 2 enable. 0: disabled 1: enabled (default)
3.0 system wake-up control (swc) (continued) 100 www.national.com 3.4.14 wake-up extension 2 enable register 1 (wk_x2en1) this register is set to ffh on power-up of v pp or software reset. it controls the routing of raw wake-up events to event de- tectors while v dd is not present. wake-up events that are enabled are routed to their event detectors while v dd is not present. location: bank 2, offset 1ah type: r/w bit 76543210 name gpie7 event ex. 2 enable gpie6 event ex. 2 enable gpie5 event ex. 2 enable gpie4/ ring event ex. 2 enable gpie3 event ex. 2 enable gpie2 event ex. 2 enable gpie1 event ex. 2 enable gpie0 event ex. 2 enable reset 11111111 bit description 7 gpie7 event extension 2 enable. 0: disabled 1: enabled (default) 6 gpie6 event extension 2 enable. 0: disabled 1: enabled (default) 5 gpie5 event extension 2 enable. 0: disabled 1: enabled (default) 4 gpie4/ ring event extension 2 enable. 0: disabled 1: enabled (default) 3 gpie3 event extension 2 enable. 0: disabled 1: enabled (default) 2 gpie2 event extension 2 enable. 0: disabled 1: enabled (default) 1 gpie1 event extension 2 enable. 0: disabled 1: enabled (default) 0 gpie0 event extension 2 enable. 0: disabled 1: enabled (default)
3.0 system wake-up control (swc) (continued) 101 www.national.com 3.4.15 wake-up extension 3 enable register 0 (wk_x3en0) this register is set to 00h on power-up of v pp or software reset. it controls the routing of raw wake-up events to the power button pulse generator. wake-up events that are enabled are routed to the power button pulse generator. location: bank 2, offset 1bh type: r/w bit 76543210 name reserved ceir event ex. 3 enable mouse event ex. 3 enable kbd event ex. 3 enable ri2 event ex. 3 enable ri1 event ex. 3 enable reset 00000000 bit description 7-5 reserved. 4 ceir event extension 3 enable. 0: disabled (default) 1: enabled 3 mouse event extension 3 enable. 0: disabled (default) 1: enabled 2 kbd event extension 3 enable. 0: disabled (default) 1: enabled 1 ri2 event extension 3 enable. 0: disabled (default) 1: enabled 0 ri1 event extension 3 enable. 0: disabled (default) 1: enabled
3.0 system wake-up control (swc) (continued) 102 www.national.com 3.4.16 wake-up extension 3 enable register 1 (wk_x3en1) this register is set to 00h on power-up of v pp or software reset. it controls the routing of raw wake-up events to the power button pulse generator. wake-up events that are enabled are routed to the power button pulse generator. location: bank 2, offset 1ch type: r/w bit 76543210 name gpie7 event ex. 3 enable gpie6 event ex. 3 enable gpie5 event ex. 3 enable gpie3/ ring event ex. 3 enable gpie3 event ex. 3 enable gpie2 event ex. 3 enable gpie1 event ex. 3 enable gpie0 event ex. 3 enable reset 00000000 bit description 7 gpie7 event extension 3 enable. 0: disabled (default) 1: enabled 6 gpie6 event extension 3 enable. 0: disabled (default) 1: enabled 5 gpie5 event extension 3 enable. 0: disabled (default) 1: enabled 4 gpie4/ ring event extension 3 enable. 0: disabled (default) 1: enabled 3 gpie3 event extension 3 enable. 0: disabled (default) 1: enabled 2 gpie2 event extension 3 enable. 0: disabled (default) 1: enabled 1 gpie1 event extension 3 enable. 0: disabled (default) 1: enabled 0 gpie0 event extension 3 enable. 0: disabled (default) 1: enabled
3.0 system wake-up control (swc) (continued) 103 www.national.com 3.4.17 ps/2 keyboard and mouse wake-up events the swc can be configured to detect any predetermined ps/2 keyboard or mouse activity. the detection mechanisms for keyboard and mouse events are independent. therefore, they can be operated simulta- neously with no interference. since both mechanisms are implemented by hardware, which is independent of the devices keyboard controller, the keyboard controller itself need not be activated to detect either keyboard or mouse events. keyboard wake-up events the keyboard wake-up detection mechanism can be programmed to detect: l any keystroke. l a speci?c programmable sequence of up to eight alphanumeric keystrokes (password mode). l any programmable sequence of up to 8 bytes of data received from the keyboard (special key sequence mode). to program the keyboard wake-up detection mechanism to wake-up on any keystroke, perform the following sequence: 1. put the wake-up mechanism in special key sequence mode by setting bits 3-0 of the ps2ctl register to 0001b. 2. set the ps2key0 and ps2key1 registers to 00h. this forces the wake-up detection mechanism to ignore the values of incoming data, thus causing it to wake-up on any keystroke. in password mode, the make and break bytes transmitted by the keyboard are discarded, and only the scan codes are com- pared against those programmed in the ps2keyn registers. to simplify the detection mechanism, only keys with a scan code of 1 byte can be included in the sequence to be detected. to program the keyboard wake-up detection mechanism to operate in password mode, proceed as follows: 1. set bits 3-0 of the ps2ctl register with a value that indicates the desired number of keystrokes in the sequence. the programmed value should be the number of keystrokes + 7 . for example, to wake-up on a sequence of two keys, set bits 3-0 to 9h. 2. program the appropriate subset of the ps2key0-ps2key7 registers, in sequential order, with the scan codes of the keys in the sequence. for example, if there are three keys in the sequence and the scan codes of these keys are 05h (first), 50h (second) and 44h (third), program ps2key0 to 05h, ps2key1 to 50h and ps2key2 to 44h (the scan codes are only examples). in special key sequence mode, all the bytes transmitted by the keyboard are compared against the ones programmed in the ps2keyn registers. these include the make and break bytes. this mode enables the detection of any sequence of key- strokes, including keys such as shift and alt. to program the keyboard wake-up detection mechanism to operate in special key sequence mode, proceed as follows: 1. set bits 3-0 of the ps2ctl register to a value that indicates the desired number of keystrokes in the sequence. the pro- grammed value should be the number of keystrokes + 1 . for example, to wake-up on a sequence of three received bytes, set bits 3-0 of ps2ctl to 2h. 2. program the appropriate subset of the ps2key0-ps2key7 registers in sequential order with the values of the data bytes that comprise the sequence. for example, if the number of bytes in the sequence is four and the values of these bytes are e0h (first), 5bh (second), e0h (third) and dbh (fourth), program ps2key0 to e0h, ps2key1 to 5bh, ps2key2 to e0h and ps2key3 to dbh (the byte values are only examples). mouse wake-up events the mouse wake-up detection mechanism can be programmed to detect either a mouse click or movement, a specific pro- grammable click (left or right) or double-click. to program this mechanism to wake-up on a specific event, set bits 6-4 of the ps2ctl register to the required value, ac- cording to the description of these bits in section 3.4.18.
3.0 system wake-up control (swc) (continued) 104 www.national.com 3.4.18 ps/2 protocol control register (ps2ctl) this register is set to 00h on power-up of v pp or software reset. it configures the ps/2 keyboard and mouse wake-up fea- tures. before changing bits 6-4 or 3-0, clear them to 0 and then write the new value. location: bank 0, offset 13h type: r/w 3.4.19 keyboard data shift register (kdsr) this register is set to 00h on power-up of v pp or software reset. it stores the keyboard data shifted in from the keyboard during transmission only when keyboard wake-up detection is enabled. location: bank 0, offset 16h type: ro bit 76543210 name disable parity check mouse wake-up con?guration keyboard wake-up con?guration reset 00000000 bit description 7 disable parity check. 0: enabled (default) 1: disabled 6-4 mouse wake-up con?guration. bits 6 5 4 configuration 0 0 0 disable mouse wake-up detection 0 0 1 wake-up on any mouse movement or button click 0 1 0 wake-up on left button click 0 1 1 wake-up on left button double-click 1 0 0 wake-up on right button click 1 0 1 wake-up on right button double-click 1 1 0 wake-up on any button single-click (left, right or middle) 1 1 1 wake-up on any button double-click (left, right or middle) 3-0 keyboard wake-up con?guration. bits 3 2 1 0 configuration 0 0 0 0 disable keyboard wake-up detection 0 0 0 1 to special key sequence 2-8 ps/2 scan codes, make and break (including shift and alt keys) 0 1 1 1 1 0 0 0 to password enabled with 1-8 keys make code (excluding shift and alt keys) 1 1 1 1 bit 76543210 name keyboard data reset 00000000 } }
3.0 system wake-up control (swc) (continued) 105 www.national.com 3.4.20 mouse data shift register (mdsr) this register is set to 00h on power-up of v sb or software reset. it stores the mouse data shifted in from the mouse during transmission only when mouse wake-up detection is enabled. location: bank 0, offset 17h type: ro 3.4.21 ps/2 keyboard key data registers (ps2key0 - ps2key7) eight registers (ps2key0-ps2key7) store the scan codes for the password or key sequence of the keyboard wake-up fea- ture, as follows: l ps2key0 register stores the scan code for the ?rst key in the password/key sequence. l ps2key1 register stores the scan code for the second key in the password/key sequence. l ps2key2 - ps2key7 registers store the scan codes for the third to eighth keys i n the password/key sequence. when one of these registers is set to 00h, it indicates that the value of the corresponding scan code byte is ignored (not compared). these registers are set to 00h on power-up of v pp or software reset. location: bank 0, offset 18h-1fh type: r/w bit 76543210 name reserved mouse data reset 00000000 bit 76543210 name scan code of keys 0-7 reset 00000000
3.0 system wake-up control (swc) (continued) 106 www.national.com 3.4.22 ceir wake-up control register (irwcr) this register is set to 00h on power-up of v pp or software reset. location: bank 1, offset 13h type: r/w . bit 76543210 name reserved ceir protocol select select irrx2 input invert irrxn input reserved ceir enable reset 00000000 bit description 7-6 reserved. 5-4 ceir protocol select. bits 5 4 protocol 0 0 rc5 (default) 0 1 nec/rca 1 x reserved 3 select irrx2 input. selects the irrx input. 0: irrx1 (default) 1: irrx2 2 invert irrxn input. 0: not inverted (default) 1: inverted 1 reserved. 0 ceir enable. 0: ceir is disabled (default). registers are maintained but ceir event status bit (of wk0_sts) does not re?ect ceir events. (unlike the ceir event enable bit of wk0_en that does not affect the ceir event status bit.) 1: ceir is enabled
3.0 system wake-up control (swc) (continued) 107 www.national.com 3.4.23 ceir wake-up address register (irwad) this register holds the unique address to be compared with the address contained in the incoming ceir message. if ceir is enabled (bit 0 o f the irwcr register is 1) and an address match occurs, then bit 5 o f the wk0_sts register is set to 1 (see section 3.4.2). this register is set to 00h on power-up of v pp or software reset. location: bank 1, offset 15h type: r/w 3.4.24 ceir wake-up address mask register (irwam) each bit in this register determines whether the corresponding bit in the irwad register is enabled in the address compar- ison. bits 5, 6 and 7 must be set to 1 if the rc-5 protocol is selected. this register is set to e0h on power-up of v pp or software reset. location: bank 1, offset 16h type: r/w bit 76543210 name ceir wake-up address reset 00000000 bit 76543210 name ceir wake-up address mask reset 11100000 bit description 7-0 ceir wake-up address mask. if the corresponding bit is 0, the address bit is not masked (enabled for compare). if the corresponding bit is 1, the address bit is masked (ignored during compare).
3.0 system wake-up control (swc) (continued) 108 www.national.com 3.4.25 ceir address shift register (adsr) this register holds the received address to be compared with the address contained in the irwad register. this register is set to 00h on power-up of v pp or software reset. location: bank 1, offset 17h type: ro 3.4.26 ceir wake-up range 0 registers these registers define the low and high limits of time range 0. the values are represented in units of 0.1 msec. for the rc-5 protocol, the bit cell width must fall within this range for the cell to be considered valid. the nominal cell width is 1.778 msec for a 36 khz carrier. irwtr0l and irwtr0h should be set to 10h and 14h respectively (default). for the nec protocol, the time distance between two consecutive ceir pulses that encodes a bit value of 0 must fall within this range. the nominal distance for a 0 is 1.125 msec for a 3 8 khz carrier. irwtr0l and irwtr0h should be set to 09h and 0dh respectively. irwtr0l register this register is set to 10h on power-up of v pp or software reset. location: bank 1, offset 18h type: r/w irwtr0h register this register is set to 14h on power-up of v pp or software reset. location: bank 1, offset 19h type: r/w bit 76543210 name ceir address reset 00000000 bit 76543210 name reserved ceir pulse change, range 0 , l ow limit reset 00010000 bit 76543210 name reserved ceir pulse change, range 0 , high limit reset 00010100
3.0 system wake-up control (swc) (continued) 109 www.national.com 3.4.27 ceir wake-up range 1 registers these registers define the low and high limits of time range 1. the values are represented in units of 0.1 msec. for the rc-5 protocol, the pulse width defining a half-bit cell must fall within this range in order for the cell to be considered valid. the nominal pulse width is 0.889 for a 3 8 khz carrier. irwtr1l and irwtr1h should be set to 07h and 0bh, respectively (de- fault). for the nec protocol, the time between two consecutive ceir pulses that encodes a bit value of 1 must fall within this range. the nominal time for a 1 is 2.25 msec for a 36 khz carrier. irwtr1l and irwtr1h should be set to 14h and 19h respectively. irwtr1l register this register is set to 07h on power-up of v pp or software reset. location: bank 1, offset 1ah type: r/w irwtr1h register this register is set to 0bh on power-up of v pp or software reset. location: bank 1, offset 1bh type: r/w 3.4.28 ceir wake-up range 2 registers these registers define the low and high limits of time range 2. the values are represented in units of 0.1 msec. these reg- isters are not used when the rc-5 protocol is selected. for the nec protocol, the header pulse width must fall within this range in order for the header to be considered valid. the nominal value is 9 msec for a 38 khz carrier. irwtr2l and irwtr2h should be set to 50h and 64h respectively (default). irwtr2l register this register is set to 50h on power-up of v pp or software reset. location: bank 1, offset 1ch type: r/w irwtr2h register this register is set to 64h on power-up of v pp or software reset. location: bank 1, offset 1dh type: r/w bit 76543210 name reserved ceir pulse change, range 1 , l ow limit reset 00000111 bit 76543210 name reserved ceir pulse change, range 1 , high limit reset 00001011 bit 76543210 name ceir pulse change, range 2 , l ow limit reset 01010000 bit 76543210 name ceir pulse change, range 2 , high limit reset 01100100
3.0 system wake-up control (swc) (continued) 110 www.national.com 3.4.29 ceir wake-up range 3 registers these registers define the low and high limits of time range 3. the values are represented in units of 0.1 msec. these reg- isters are not used when the rc-5 protocol is selected. for the nec protocol, the post header gap width must fall within this range in order for the gap to be considered valid. the nominal value is 4.5 msec for a 36 khz carrier. irwtr3l and irwtr3h should be set to 28h and 32h respectively (default). irwtr3l register this register is set to 28h on power-up of v pp or software reset. location: bank1, offset 1eh type: r/ws irwtr3h register this register is set to 32h on power-up of v pp or software reset. location: bank 1, offset 1fh type: r/w ceir recommended values table 43 lists the recommended time ranges limits for the different protocols and their four applicable ranges. the values are represented in hexadecimal code where the units are of 0.1 msec. bit 76543210 name ceir pulse change, range 3 , l ow limit reset 00101000 bit 76543210 name ceir pulse change, range 3 , high limit reset 00110010 table 43. time range limits for ceir protocols range rc-5 nec rca low limit high limit low limit high limit low limit high limit 0 10h 14h 09h 0dh 0ch 12h 1 07h 0bh 14h 19h 16h 1ch 2 -- 50h 64h b4h dch 3 -- 28h 32h 23h 2dh
3.0 system wake-up control (swc) (continued) 111 www.national.com 3.4.30 standby general-purpose i/o (sbgpio) register overview the swc can be used to operate up to 12 v sb -powered general-purpose input/output (gpio), input (gpi) or output (gpo) pins, eight of which support event detection. these are as follows: l gpioe0-5 are gpio pins. l gpie6,7 and gpis2,3 are gpi pins. l gpos0,1 are gpo pins. for programming convenience, these pins are associated with two sbgpio ports. specifically, gpie0-5 and gpie6,7 are associated with bits 0 t o 7 o f sbgpio port 0, respectively, and gpos0,1 and gpis2,3 are associated with bits 0 t o 3 o f sbgpio port 1, respectively. table 44 provides a summary of the sbgpio pin-to-port assignment and pin types. table 44. sbgpio pin types and associated port an sbgpio port is structured as an 8-bit port, based on eight pins. it features: ? software capability to manipulate and read pin levels. ? controllable system noti?cation by several means based on the pin levels t ransition. ? ability to capture and manipulate events and their associated status. ? back-drive protected pins. sbgpio port operation is associated with two sets of registers: ? pin con?guration registers, mapped in the swc register bank 3. these registers are used to statically set up the log- ical behavior of each pin. there is one 8-bit register for each sbgpio pin. ? two 8-bit runtime registers: sbgpio data out (sbgpdo) and sbgpio data in (sbgpdi). these registers are mapped in the swc device i/o space (determined by the base address registers in the swc device con?guration). they are used to manipulate and/or read the pin values. each runtime register corresponds to the 8-pin port de- scribed above (see table 44). each sbgpio pin is associated with up to six configuration bits and the corresponding bit slice of the two runtime registers, as shown in figure 10. the sbgpio port has basic as well as enhanced functionality. basic functionality includes the manipulation and reading of the sbgpio pins, as described in section 6.2 on page 130. enhanced functionality includes event detection, as described in event detection on page 113. pin(s) port type event detection gpioe0-5 0 i/o yes gpie6,7 0 i yes gpos0,1 1 o no gpis2,3 1 i no
3.0 system wake-up control (swc) (continued) 112 www.national.com figure 10. sbgpio port architecture basic functionality the basic functionality of each sbgpio pin is based on four configuration bits and a bit slice of runtime registers sbgpdo and sbgpdi. the configuration and operation of a single pin (pin n in port x) is shown in figure 11. figure 11. sbgpio basic functionality sbgpio pin sbgpio pin select register con?guration register sbgpdox sbgpdix runtime registers sbgpiox base address event bit n port and pin 8 sbgpio pin con?guration registers x8 sbgpio port x pin n x8 sbgpioxn cnfg x8 sbgpioxn pin logic x = port number n = pin number, 0 to 7 pending indicator select to wake-up logic pin data out data in output enable output internal bus lock type static pull-up pull-up enable sbgpio pin con?guration register push-pull=1 pull-up control read only read/write bit 3 bit 2 bit 1 bit 0
3.0 system wake-up control (swc) (continued) 113 www.national.com con?guration options the sbgpio pin configuration register controls the following basic configuration options: ? pin direction - controlled by output enable (bit 0). ? output type - push-pull vs. open-drain. it is controlled by output type (bit 1) by enabling/disabling the pull-up portion of the output buffer. ? weak static pull-up - may be added to any type of port (input, open-drain or totem pole). it is controlled by pull-up control (bit 2). ? pin lock - a gpio pin may be locked to prevent any changes in the output value and/or the output characteristics. the lock is controlled by lock (bit 3). it disables writes to the sbgpdo register bits and to bits 0-3 of the standby gpio pin configuration register (including the lock bit itself). once locked, it can be released by hardware reset only. operation the value that is written to the sbgpdo register is driven to the pin, if the output is enabled. reading from the sbgpdo register returns its contents, regardless of the pin value or the port configuration. the sbgpdi register is a read-only register. reading from the sbgpdi register returns the pin value, regardless of what is driving it (the port itself, configured as an output port, or the external device when the port is configured as an input port). writing to this register is ignored. activation of the sbgpio port is controlled by the same external, device-specific configuration bit (or a combination of bits) that control the activation of the swc. when the swc logical device is inactive, access to both the sbgpdi and sbgpdo registers is disabled. however, there is no change in the port configuration and in the sbgpdo value and hence there is no effect on the outputs of the pins. event detection the enhanced sbgpio port supports input event detection. this functionality is based on three configuration bits. the con- figuration and operation of the event detection capability is shown in figure 12. an swc status register reflects the status of each input event. swc configuration registers determine the effect of each input event on the various means of system notification available in the swc. figure 12. event detection event enable event polarity detected enabled events sbgpio pins input debouncer event internal bus 0 1 pin r/w 1 to clear status rising edge =1 rising edge detector from other sbgpio pin con?guration register event debounce enable r/w bit 6 bit 5 indicator pending
3.0 system wake-up control (swc) (continued) 114 www.national.com event con?guration each pin in the sbgpio port is a potential input event source. the event detection can trigger a system notification upon predeter- mined behavior of the source pin. the sbgpio pin configuration register determines the event detection trigger type for the system notification. ? event type and polarity - one trigger type of event detection is supported: edge (event type, bit 4 = 0). an edge event may be detected upon a source pin transition either from high to low or low to high. the direction of the transition (i.e., edge) is determined by event polarity (bit 5). ? event debounce enable - the input signal can be debounced for about 15 msec before entering the detector. the signal state is transferred to the detector only after a debouncing period during which the signal has no transitions, to ensure that the signal is stable. the debouncer adds 15 msec delay to both assertion and de-assertion of the event pending indicator. therefore, when working with a level event and system notification by either smi or irq, it is recommended to disable the debounce if the delay in the smi/irq de-assertion is not acceptable. the debounce is controlled by event debounce enable (bit 6 of the sbgpio pin configuration register). 3.4.31 standby gpio pin select register (sbgpsel) this register selects the gpioe/gpie pin (port number and pin number) to be configured (the register accessed by the standby gpio pin configuration register). this register is reset to 00h on v pp power-up or software reset. when port 0 i s selected, bits 2-0 select between pins gpie7,6 and gpioe5-0. when port 1 i s selected, bits 2-0 select be- tween pins gpos0 and gpos1. pins gpis2 and gpis3 are input only and require no configuration. location: bank 3, offset 13h type: r/w bit 76543210 name reserved port select reserved pin select reset 00000000 bit description 7-5 reserved. 4 port select. this bit selects the gpio port t o b e con?gured. 0: port 0 (default) 1: port 1 3 reserved. 2-0 pin select . these bits select the gpio pin to be con?gured in the selected port. 000, 001, ... 111:the binary value of the pin number, 0 , 1 , ... 7 respectively (default=0)
3.0 system wake-up control (swc) (continued) 115 www.national.com 3.4.32 standby gpio pin configuration register (sbgpcfg) this is a group of 12 configuration registers. eight are identical for gpioe and gpie, two are identical for gpos and two are identical for gpis. each gpioe/gpie register is associated with one gpioe/gpie pin, and each gpos and gpis reg- ister is associated with one gpos or gpis pin. the entire set is mapped to the same address. the mapping scheme is based on the standby gpio pin select (sbgpsel) register that functions as an index register and the specific standby gpio pin configuration register that reflects the configuration of the currently selected pin. bits 0-3 are applicable only for pins gpioe0-5 and gpos0,1. bits 4-6 are applicable for all gpioe/gpie pins. location: bank 3, offset 14h type: r/w (bit 3 is set only) for gpioe and gpie: for gpos: for gpis: bit 76543210 name reserved event debounce enable event polarity event type lock pull-up control output type output enable reset 01000100 bit 76543210 name reserved lock pull-up control output type output enable reset 00000101 bit 76543210 name reserved reset 00000000 bit description 7 reserved. (for gpos and gpis, bits 7-4 and 7-0 are reserved, respectively). 6 event debounce enable. 0: disabled 1: enabled (default) 5 event polarity. this bit de?nes the polarity of the signal that causes a detection of an event from the corresponding gpio pin. 0: falling edge input (default) 1: rising edge input 4 event type. this bit de?nes the signal type that causes a detection of an event from the corresponding gpio pin. 0: edge input (default) 1: reserved 3 lock . this bit locks bits 2-0 of this register. these bits are associated with the gpio pin currently selected by the sbgpsel register. once this bit is set to 1 by software, i t can only be cleared to 0 by v sb power-up reset. 0: no effect (default at v sb power-up reset) 1: direction, output type, pull-up and output value locked
3.0 system wake-up control (swc) (continued) 116 www.national.com 2 pull-up control. this bit is used to enable/disable the internal pull-up capability of the corresponding gpio pin. it supports open-drain output signals with internal pull-ups and ttl input signals. 0: disabled 1: enabled (default) 1 output type. this bit controls the output buffer type (open-drain or totem pole) of the corresponding gpio pin. 0: open-drain (default) 1: push-pull 0 output enable. for gpos, this is a r/o bit. it indicates the gpos pin output state and is always 1 . for gpioe and gpie, this bit indicates the gpio pin output state. i t has no effect on input. 0: tri-state (default for gpioe/gpie) 1: output enabled (default for gpos) bit description
3.0 system wake-up control (swc) (continued) 117 www.national.com 3.4.33 standby gpioe/gpie data out register 0 (sb_gpdo0) this register is set to 3fh on v pp power-up or software reset only when the lock bit of the sbgpcfg register is set to 0. it determines the value to be driven on the gpioe pins when configured as outputs. location: offset 08h type: r/w 3.4.34 standby gpioe/gpie data in register 0 (sb_gpdi0) this register reflects the values of the gpie7-6 and gpioe5-0 pins. write to this register is ignored. location: offset 09h type: ro bit 76543210 name reserved data out reset 00111111 bit description 7-6 reserved. 5 data out. bits 5-0 correspond to pins gpioe5-0 respectively. the value of each bit determines the value driven on the corresponding gpioe pin when its output buffer is enabled. writing to the bit latches the written data unless the bit is locked by the corresponding gpioe con?guration lock bit. reading the bit returns its value, regardless of the pin value and con?guration. 0: corresponding pin level l ow when output enabled 1: corresponding pin level high (according to buffer type and static pull-up selection) when output enabled 4 3 2 1 0 bit 76543210 name data in reset xxxxxxxx bit description 7 data in. bits 7-0 correspond to pins gpie7-6 and gpioe5-0 respectively. reading each bit returns the value of the corresponding gpie/gpioe pin regardless of the pin con?guration and the sb0_gpdo register value. 0: corresponding pin level l ow 1: corresponding pin level high 6 5 4 3 2 1 0
3.0 system wake-up control (swc) (continued) 118 www.national.com 3.4.35 standby gpos data out register 1 (sb_gpdo1) this register is set to 03h on v pp power-up or software reset only when the lock bit of the sbgpcfg register is set to 0. it determines the value to be driven on the gpso0,1 pins. location: offset 0ah type: r/w 3.4.36 standby gpis data in register 1 (sb_gpdi1) this register reflects the values of the gpos0,1 and gpis2,3 pins. write to this register is ignored. location: offset 0bh type: ro bit 76543210 name reserved data out reset 00000011 bit description 7-2 reserved. 1-0 data out. bits 1-0 correspond to pins gpos1-0 respectively. the value of each bit determines the value driven on the corresponding gpos pin when its output buffer is enabled. writing to the bit latches the written data unless the bit is locked by the corresponding gpos con?guration lock bit. reading the bit returns its value, regardless of the pin value and con?guration. 0: corresponding pin level l ow 1: corresponding pin level high (according to buffer type and static pull-up selection) bit 76543210 name reserved data in reset xxxxxxxx bit description 7-4 reserved. 3-0 data in. reading each bit returns the value of the corresponding gpos/gpis pin. 0: corresponding pin level l ow 1: corresponding pin level high
3.0 system wake-up control (swc) (continued) 119 www.national.com 3.5 swc register bitmap table 45. banks 0 and 1 - the common register bitmap table 46. bank 0 - ps/2 keyboard/mouse wake-up con?guration and control registers bitmap register bits offset mnemonic 7 6 5 4 3 2 1 0 00h wk_sts0 module irq event status software event status gpio event status ceir event status mouse event status kbd event status ri2 event status ri1 event status 01h wk_sts1 gpie7 event status gpie6 event status gpie5 event status gpie4/ ring event status gpie3 event status gpie2 event status gpie1 event status gpie0 event status 02h wk_en0 module irq event enable software event enable gpio event enable ceir event enable mouse event enable kbd event enable ri2 event enable ri1 event enable 03h wk_en1 gpie7 event enable gpie6 event enable gpie5 event enable gpie4/ ring event enable gpie3 event enable gpie2 event enable gpie1 event enable gpie0 event enable 04h wk_cfg reserved enable power but- ton pulse on s3 swap kbc inputs con?guration bank select 05h-07h reserved 08h sb_gpdo0 reserved data out 09h sb_gpdi0 data in 0ah sb_gpdo1 reserved data out 0bh sb_gpdi1 reserved data in 0ch-12h reserved register bits offset mnemonic 7 6 5 4 3 2 1 0 13h ps2ctl disable parity mouse wake-up con?guration keyboard wake-up con?guration 16h kdsr keyboard data 17h mdsr reserved mouse data 18h-1fh ps2key0- ps2key7 scan code of keys 0-7
3.0 system wake-up control (swc) (continued) 120 www.national.com table 47. bank 1 - ceir wake-up con?guration and control registers bitmap table 48. bank 2 - event routing control registers bitmap register bits offset mnemonic 76543210 13h irwcr reserved ceir protocol select select irrx2 input invert irrxn input reserved ceir enable 14h reserved 15h irwad ceir wake-up address 16h irwam ceir wake-up address mask 17h adsr ceir address 18h irwtr0l reserved ceir pulse change, range 0, low limit 19h irwtr0h reserved ceir pulse change, range 0, high limit 1ah irwtr1l reserved ceir pulse change, range 1, low limit 1bh irwtr1h reserved ceir pulse change, range 1, high limit 1ch irwtr2l ceir pulse change, range 2, low limit 1dh irwtr2h ceir pulse change, range 2, high limit 1eh irwtr3l ceir pulse change, range 3, low limit 1fh irwtr3h ceir pulse change, range 3, high limit register bits offset mnemonic 7 6 5 4 3 2 1 0 13h wk_smien0 reserved software event to smi enable reserved ceir event to smi enable mouse event to smi enable kbd event to smi enable ri2 event to smi enable ri1 event to smi enable 14h wk_smien1 gpie7 event to smi enable gpie6 event to smi enable gpie5 event to smi enable gpie4/ ring event to smi enable gpie3 event to smi enable gpie2 event to smi enable gpie1 event to smi enable gpie0 event to smi enable 15h wk_irqen0 reserved software event to irq enable reserved ceir event to irq enable mouse event to irq enable kbd event to irq enable ri2 event to irq enable ri1 event to irq enable 16h wk_irqen1 gpie7 event to irq enable gpie6 event to irq enable gpie5 event to irq enable gpie4/ ring event to irq enable gpie3 event to irq enable gpie2 event to irq enable gpie1 event to irq enable gpie0 event to irq enable 17h wk_x1en0 reserved ceir event ex. 1 enable mouse event ex. 1 enable kbd event ex. 1 enable ri2 event ex. 1 enable ri1 event ex. 1 enable 18h wk_x1en1 gpie7 event ex. 1 enable gpie6 event ex. 1 enable gpie5 event ex. 1 enable gpie4/ ring event ex. 1 enable gpie3 event ex. 1 enable gpie2 event ex. 1 enable gpie1 event ex. 1 enable gpie0 event ex. 1 enable 19h wk_x2en0 reserved ceir event ex. 2 enable mouse event ex. 2 enable kbd event ex. 2 enable ri2 event ex. 2 enable ri1 event ex. 2 enable
3.0 system wake-up control (swc) (continued) 121 www.national.com table 49. bank 3 - standby general-purpose i/o con?guration registers bitmap 1ah wk_x2en1 gpie7 event ex. 2 enable gpie6 event ex. 2 enable gpie5 event ex. 2 enable gpie4/ ring event ex. 2 enable gpie3 event ex. 2 enable gpie2 event ex. 2 enable gpie1 event ex. 2 enable gpie0 event ex. 2 enable 1bh wk_x3en0 reserved ceir event ex. 3 enable mouse event ex. 3 enable kbd event ex. 3 enable ri2 event ex. 3 enable ri1 event ex. 3 enable 1ch wk_x3en1 gpie7 event ex. 3 enable gpie6 event ex. 3 enable gpie5 event ex. 3 enable gpie4/ ring event ex. 3 enable gpie3 event ex. 3 enable gpie2 event ex. 3 enable gpie1 event ex. 3 enable gpie0 event ex. 3 enable 1dh- 1fh reserved register bits offset mnemonic 7 6 5 4 3 2 1 0 13h sbgpsel reserved port select reserved pin select 14h sbgpcfg reserved event debounce enable event polarity event type lock pull-up control output type output enable 15h- 1fh reserved
122 www.national.com 4.0 fan speed control 4.1 overview this chapter describes a generic fan speed control module. for the implementation used in this device, see the de vice architecture and con?gur ation chapter. the fan speed control is a programmable pulse width modulation (pwm) generator. the pwm generator output is used to control the fans power voltage, which is correlated to the fans speed. convertin ga0to 100% duty cycle pwm signal to an analog voltage range is achieved by an external circuit, as shown in figure 13. some newer fans accept direct pwm input without any external circuitry. when an overtemperature condition is detected, the fan speed control forces the fan to turn on at 100% duty cycle. figure 13. fan speed control - system con?guration 4.2 functional description the pwm generator operation is based on a pwm counter and two registers: the fan speed control pre-scale register (fcpsr), used to determine the overall cycle time (or the frequency) of the fanout output, and the fan speed control duty cycle register (fcdcr), used to determine the duty cycle of the fanout between 0 to 100%. the pwm counter is an 8-bit, free-running counter that runs continuously in a cyclic manner, i.e., its cycle equals 256 clock periods. the pwm output is high, as long as the count is lower than the fcdcr value and it flips to low as the counter ex- ceeds that value. the duty cycle (expressed as a percentage) is therefore (fcdcr/256)*100. in particular, the pwm output is continuously low when fcdcr=0 and continuously high when fcdcr=ffh. the fanout output may be inverted by an external configuration bit, in which case the fanout duty cycle is ([256-fcdcr]/256)*100. the pwm counter clock is generated by dividing the input clock (either 24 mhz or 200 khz), using a clock divider. the di- vision factor, which must be between 1 and 124, is defined as pre-scale value+1, where pre-scale is the binary value stored in bits 6 to 0 of the fcpsr register. the resulting pwm output frequency is therefore: (24 mhz or 200 khz/([pre-scale value+1] * 256). the default selection of 24 mhz input clock allows a programmable fanout frequency in the range of 756 hz to 93.75 khz. for lower frequencies, selecting the 200 khz input clock allows a frequency range of 6 hz to 781 hz (see figure 14). the fanout frequency must be pre-selected according to the fan types specific requirements prior to enabling the fan speed control. the only run-time change that is required to dynamically control the fan speed is the value of the fcdcr register. warning! the contents of the fcpsr register must not be changed when the fan speed control is enabled. enable fans on ots detection when the respective fan i enable on ots (bits 2-0) of the fan speed control ots con- figuration register is set (see section 2.17.5 on page 76), the fan is forced to 100% duty cycle when any of the temperature measurement channels flags an overtemperature condition. this occurs regardless of the setting of the fcdcr register in order to help protect the system from overheating. fan speed control fan fanout control external circuitry external circuitry 24 mhz (1-124) pwm fcdcr register fcdcr > counter fanout fcpsr register figure 14. pwm generator (fanout) o invert 0 1 200 khz bit 7 bits 6-0 pwm output - counter comparator 0 1 fanout clock divider
4.0 fan speed control (continued) 123 www.national.com 4.3 fan speed control registers the following abbreviations are used to indicate the register type: ? r/w = read/write. ? r = read from a speci?c address returns the value of a speci?c register. w rite to the same address is to a different register. ? w = w rite. ? ro = read only. ? r/w1c = read/write 1 t o clear. w riting 1 t o a bit clears it to 0. writing 0 has no effect. 4.3.1 fan speed control register map 4.3.2 fan speed control pre-scale register (fcpsr) location: device specific type: r/w offset mnemonic register name type section device speci?c 1 1. the location of this register is defined in the de vice architecture and con?gur ation chapter. fcpsr fan speed control pre-scale r/w 4.3.2 device speci?c 1 fcdcr fan speed control duty cycle r/w 4.3.3 bit 76543210 name clock select pre-scale value reset 00000000 bit description 7 clock select. this bit selects the input clock for the clock divider. 0: 24 mhz 1: 200 khz 6-0 pre-scale value. the clock divider for the input clock (24 mhz or 200 khz) is pre-scale value + 1 . w riting 0000000b to these bits transfers the input clock directly to the counter. the maximum clock divider is 124 (7bh +1). these bits must not be programmed with the values 7ch, 7dh, 7eh and 7fh as this may produce unpredictable results. the contents of this register should not be changed when the corresponding fan speed control enable bit of the fan speed control con?guration register is 1 (see de vice architecture and con?gur ation chapter) as this may produce unpredictable results.
4.0 fan speed control (continued) 124 www.national.com 4.3.3 fan speed control duty cycle register (fcdcr) location: device specific type: r/w 4.4 fan speed control bitmap bit 76543210 name duty cycle value reset 11111111 bit description 7-0 duty cycle. the binary value of this 8-bit ?eld determines the number of clock cycles out of a 256-cycle period, during which the pwm output is high (while fanout is either equal to or the inverse of the pwm output, depending on the inverse fanout con?guration bit). 00h: pwm output is continuously low 01h - feh: pwm output is high for [duty cycle value] clock cycles and low for [256-duty cycle value] clock cycles ffh: pwm output is continuously high register bits offset mnemonic 76543210 device specific 1 1. the location of this register is de?ned in the de vice architecture and con?gur ation chapter. fcpsr clock select pre-scale value device specific 1 fcdcr duty cycle value
125 www.national.com 5.0 fan speed monitor 5.1 overview this chapter describes a generic fan speed monitor module. for the implementation used in this device, see the de vice architecture and con?gur ation chapter. the fan speed monitor determines the fans speed by measuring the time between consecutive tachometer pulses emitted by the fan once or twice per revolution (depending on the fan type). it may provide the system with a current speed reading and/or alert the system, by interrupt, whenever the speed drops below a programmable threshold. the fan speed monitor indicates whether the speed is just below the threshold or inefficiently low to consider the fan stopped. figure 15 shows the basic system configuration of the fan speed monitor. figure 15. fan speed monitor - system con?guration 5.2 functional description the fan emits a tachometer pulse every half or full revolution (depending on the fan type). these pulses are fed into the fan speed monitor through the fanin input pin. measuring the time between these pulses is the basis for speed monitoring. ncbtp is defined as the number of clock-cycles between consecutive tachometer pulses. for a known clock rate (f hz) and number of pulses per revolution (n=1,2), the fan speed is calculated according to the following relationship: fan speed (in rpm) = the fan speed monitor consists of an 8-bit counter to measure the ncbtp and three 8-bit registers: fan monitor speed register (fmspr), fan monitor threshold register (fmthr) and fan monitor control and status register (fmcsr). figure 16 is a general block diagram of the fan speed monitor. the up counter and the fmspr register are cleared to 0 while the fan speed monitor is disabled (and in particular upon system reset). when the fan speed monitor is enabled and there is no counter overflow, the counter runs (up-counts), clocked by the se- lected clock rate. starting from the second fanin pulse (after activation) and upon every rising edge of fanin when the over threshold bit is 0, the fmspr register is loaded with the contents of the counter, the counter is cleared to 0 and the speed ready bit is set to 1. upon reading fmspr, the speed ready bit of the fmcsr is cleared to 0. the above operation continually repeats itself, providing the host with the current speed reading, as long as the fmspr register value is lower than the threshold. once the loaded fmspr register value exceeds the threshold, the over threshold bit is set to 1. interrupt is asserted if enabled. the fmspr register is not loaded with any new values when the over threshold bit is set. a new value is loaded only after clearing the over threshold bit (by writing 1) and reading the fmspr register. this guarantees that the same ncbtp value that generated the interrupt remains available for the interrupt handler. if the counter passes ffh, the overflow bit is set to 1, the fmspr register is cleared and the interrupt is asserted, if enabled. the overflow bit is cleared to 0 when it is written with 1, after which speed measurement resumes. the input buffer of the fanin signal is a hysteresis buffer (schmitt trigger). this signal passes through a digital filter when the filter disable bit (bit 4 o f the fmcsr register) is 0 . the digital filter uses a 3 2 khz clock to filter out any pulses shorter than 750 m sec. this filter can be by-passed when setting bit 4 of the fmcsr register to 1. fan speed fanin fan tachometer pulse filtering circuitry monitor (optional) 60 f ncbtp n ------------------------------
5.0 fan speed monitor (continued) 126 www.national.com . figure 16. fan speed monitor 5.3 fan speed monitor registers the fmspr register is used to hold the current speed reading (which is represented by the latest ncbtp and refreshed upon every fanin pulse). the fmthr register holds the maximum allowed ncbtp value (representing the slowest speed at which the fan is allowed to operate) without causing system alert. additional control and status bits are available through the fmcsr register. these include: ? over threshold. a status bit that indicates that the ncbtp has exceeded the threshold (the speed has dropped below the allowed minimum). ? overflow. a status bit that indicates that the ncbtp is higher than ffh. with a proper input clock selection, this means that the speed is inefficiently low and is considered stopped. ? speed ready. a status bit that indicates that new, valid data has been loaded into the fmspr register. ? clock select. a 2-bit control field that selects the counter clock rate as either 2 khz, 4 khz, 8 khz or 16 khz. the following abbreviations are used to indicate the register type: ? r/w = read/write. ? r = read from a speci?c address returns the value of a speci?c register. w rite to the same address is to a different register. ? w = w rite. ? ro = read only. ? r/w1c = read/write 1 t o clear. w riting 1 t o a bit clears it to 0. writing 0 has no effect. 5.3.1 fan speed monitor register map offset mnemonic register name type section device specific 1 1. the location of this register is de?ned in the de vice architecture and con?gur ation chapter. fmthr fan monitor threshold r/w 5.3.2 device specific 1 fmspr fan monitor speed ro 5.3.3 device specific 1 fmcsr fan monitor control and status varies per bit 5.3.4 fmspr register clock select fanin filter (fmcsr, bit 4) pos. edge detector over?ow (fmcsr, bit 2) up counter 16 khz 8 khz 4 khz 2 khz fmthr register comparator over (fmcsr, bit 1) threshold clear load interrupt enable (fmcsr, bit 3) interrupt (fmcsr, bits 6-5) filter disable (fmcsr, bit 0) speed ready set clock
5.0 fan speed monitor (continued) 127 www.national.com 5.3.2 fan monitor threshold register (fmthr) this 8-bit register contains the programmable threshold for the fan. this threshold is the maximum number of clock cycles between consecutive tachometer pulses (frequencies of 16, 8, 4 o r 2 khz). it represents the minimum fan speed permitted in the system. if the period between consecutive tachometer pulses is greater than the threshold, an interrupt (if enabled) is issued. after reset, the value of fmthr is ffh. this register should not be changed when the corresponding fan monitor enable bit is set to 1 (enabled), since this may cause unpredictable results. location: device specific type: r/w 5.3.3 fan monitor speed register (fmspr) this read-only 8-bit register holds the speed reading, represented by number of clock cycles between consecutive tachom- eter pulses. for details, refer to section 5.2. when the speed ready bit of the fmcsr register is 1, fmspr holds valid data that has not yet been read. it is cleared to 00h upon any of the following conditions: l system reset. l fan monitor enable bit is set to 0. l over?ow bit is set to 1. location: device specific type: ro 5.3.4 fan monitor control and status register (fmcsr) location: device specific type: varies per bit bit 76543210 name threshold value reset 11111111 bit 76543210 name fan speed reading reset 00000000 bit 76543210 name reserved clock select filter disable interrupt enable over?ow over threshold speed ready reset 00100000
5.0 fan speed monitor (continued) 128 www.national.com 5.4 fan speed monitor bitmap bit type description 7 reserved 6-5 r/w clock select. selects the clock source provided to the counter. these bits must not be changed when the corresponding fan monitor enable bit is 1 (enabled). 00: 16 khz 01: 8 khz (default) 10: 4 khz 11: 2 khz 4 r/w filter disable . when this bit is set to 1, the digital ?lter is disabled. when it is cleared, the ?lter is enabled. this bit should not be changed when the corresponding fan monitor enable bit is 1 (enabled) to avoid unpredictable results. 0: digital ?lter enabled (default) 1: digital ?lter disabled 3 r/w interrupt enable . this bit controls the assertion of over?ow interrupt and over threshold interrupt. 0: interrupt disabled (default) 1: interrupt enabled. interrupt is asserted when an over threshold bit, over?ow bit or both are set to 1. 2 r/w1c over?ow . indicates that the counter has passed ffh and the fan speed is inef?ciently slow; i.e., slower than 60 * f/(256 * n). writing 1 t o this bit clears it to 0. 0: no over?ow occurred since the last time this bit was cleared (by reset or by writing 1) 1: counter passed ffh 1 r/w1c over threshold . indicates that the value loaded into the fmspr register upon detection of the rising edge of the fanin pulse exceeded the threshold value. 0: fmspr register value did not exceed the threshold since the last time this bit was cleared (by reset or by writing 1) 1: fmspr register value exceeded the threshold 0ro speed ready . this bit indicates that the speed register holds new (not yet read) and valid data. it is set to 1 o n each rising edge of the fanin input (starting from the second one) if the over threshold bit is 0. it is cleared to 0 whenever the speed register is read or when the overflow bit is set. 0: no new valid data in the fmspr register (data is either invalid or has already been read) 1: fmspr register loaded with new and valid data register bits offset mnemonic 7 6 5 43210 device speci?c 1 1. the location of this register is de?ned in the de vice architecture and con?gur ation chapter. fmthr threshold value device speci?c 1 fmspr fan speed reading device speci?c 1 fmcsr reserved clock select filter disable interrupt enable over?ow over threshold speed ready
129 www.national.com 6.0 general-purpose input/output (gpio) port this chapter describes one 8-bit port. a device may include a combination of several ports with different implementations. for the device specific implementation, see the device architecture and configuration chapter. 6.1 overview the gpio port is an 8-bit port, which is based on eight pins. it features: l software capability to manipulate and read pin levels. l controllable system noti?cation by several means based on the pin level o r l evel transition. l ability to capture and manipulate events and their associated status. l back-drive protected pins. gpio port operation is associated with two sets of registers: l pin con?guration registers, mapped in the device con?guration space. these registers are used to statically set up the logical behavior of each pin. there are two 8-bit register for each gpio pin. l four 8-bit runtime registers: gpio data out (gpdo), gpio data in (gpdi), gpio event enable (gpeven) and gpio event status (gpevst). these registers are mapped in the gpio device io space (which is determined by the base address registers in the gpio device con?guration). they are used to manipulate and/or read the pin val- ues and to control and handle system noti?cation. each runtime register corresponds to the 8-pin port, such that bit n in each one of the four registers is associated with gpioxn pin, where x is the port number. each gpio pin is associated with ten configuration bits and the corresponding bit slice of the four runtime registers, as shown in figure 17. the functionality of the gpio port is divided into basic functionality (which includes the manipulation and reading of the gpio pins) and enhanced functionality (which includes event detection and system notification). basic functionality is described in section 6.2. enhanced functionality is described in section 6.3. figure 17. gpio port architecture gpio pin gpio pin select (gpsel) con?guration (gpcfg) gpdox gpdix gpevenx gpevstx runtime registers gpiox base address event bit n port and pin 8 gpcfg registers x8 gpioxn pin x8 gpioxn cnfg interrupt x8 gpioxn port logic x = port number n = pin number, 0 to 7 pending indicator request smi pwureq gpio pin event routing (gpevr) 8 gpevr registers gpioxn route select event routing control register register register
6.0 general-purpose input/output (gpio) port (continued) 130 www.national.com 6.2 basic functionality the basic functionality of each gpio pin is based on four configuration bits and a bit slice of runtime registers gpdo and gpdi. the configuration and operation of a single pin gpioxn (pin n in port x) is shown in figure 18. figure 18. gpio basic functionality 6.2.1 configuration options the gpcfg register controls the following basic configuration options: ? port direction - controlled by the output enable bit (bit 0). ? output type - push-pull vs. open-drain. it is controlled by output buffer type (bit 1) by enabling/disabling the pull-up portion of the output buffer. ? weak static pull-up - may be added to any type of port (input, open-drain or push-pull). it is controlled by pull-up control (bit 2). ? pin lock - gpio pin may be locked to prevent any changes in the output value and/or the output characteristics. the lock is controlled by lock (bit 3). it disables writes to the gpdo register bits and to bits 0-3 of the gpcfg register (in- cluding the lock bit itself). once locked, it can be released by hardware reset only. 6.2.2 operation the value that is written to the gpdo register is driven to the pin if the output is enabled. reading from the gpdo register returns its contents regardless of the pin value or the port configuration. the gpdi register is a read-only register. reading from the gpdi register returns the pin value regardless of what is driving it (the port itself, configured as an output port, or the external device when the port is configured as an input port). writing to this register is ignored. activation of the gpio port is controlled by external device specific configuration bit (or a combination of bits). when the port is inactive, access to gpdi and gpdo registers is disabled and the inputs are blocked. however, there is no change in the port configuration and in the gpdo value and hence there is no effect on the outputs of the pins. gpio device pin data out data in enable output enable output internal bus lock type static pull-up pull-up enable gpio pin con?guration (gpcfg) register push-pull =1 pull-up control read only read/write bit 3 bit 2 bit 1 bit 0
6.0 general-purpose input/output (gpio) port (continued) 131 www.national.com 6.3 event handling and system notification the enhanced gpio port supports system notification based on event detection. this functionality is based on six configu- ration bits and a bit slice of runtime registers gpeven and gpevst. the configuration and operation of the event detection capability is shown in figure 19. the operation of system notification is illustrated in figure 20. figure 19. event detection 6.3.1 event configuration each pin in the gpio port is a potential input event source. the event detection can trigger a system notification upon pre- determined behavior of the source pin. the gpcfg register determines the event detection trigger type for the system no- tification. event type and polarity two trigger types of event detection are supported: edge and level. an edge event may be detected upon a source pin tran- sition either from high to low or low to high. a level event may be detected when the source pin is in active level. the trigger type is determined by event type (bit 4 o f the gpcfg register). the direction of the transition (for edge) or the polarity of the active level (for level) is determined by event polarity (bit 5 of the gpcfg register). event debounce enable the input signal can be debounced for about 15 msec before entering the detector. to ensure that the signal is stable, the signal state is transferred to the detector only after a debouncing period, during which the signal has no transitions. the debouncer adds 15 msec delay to both assertion and de-assertion of the event pending indicator. therefore, when working with a level event and system notification by either smi or irq, it is recommended to disable the debounce if the delay in the smi/irq de-assertion is not acceptable. the debounce is controlled by event debounce enable (bit 6 o f the gpcfg register). 6.3.2 system notification system notification on gpio-triggered events is by means of assertion of one or more of the following output pins: l interrupt request (via the devices bus interface). l system management interrupt ( smi, via the devices bus interface). l power-up request ( pwureq, via the system wake-up control). the system notification for each gpio pin is controlled by the corresponding bits in the gpeven and gpevr registers. system notification by a gpio pin is enabled if the corresponding bit of the gpeven register is set to 1. the corresponding bits in the gpevr register select which means of system notification the detected event is routed to. the event routing mechanism is described in figure 20. event enable event polarity detected enabled events gpio pins input debouncer 1 0 event internal bus 0 1 pin level =1 r/w 1 to clear status rising edge or rising edge detector from other high level =1 gpio pin con?guration register event type event debounce enable r/w bit 6 bit 5 bit 4 indicator pending
6.0 general-purpose input/output (gpio) port (continued) 132 www.national.com figure 20. gpio event routing mechanism the gpevst register is a general-purpose edge detector that may be used to reflect the event source pending status for edge-triggered events. the term active edge refers to a change in a gpio pin level that matches the event polarity bit (1 for rising edge and 0 for falling edge). active level refers to the gpio pin level that matches the event polarity bit (1 for high level and 0 for low level). the corresponding bit of the gpevst register is set by hardware whenever an active edge is detected regardless of any other bit settings. writing 1 to the status bit clears it to 0. writing 0 is ignored. a gpio pin is in event pending state if the corresponding bit of the gpeven register is set and either: l the event type is level and the pin is in active l evel, or l the event type is edge and the corresponding bit of the gpevst register is set. the target means of system notification is asserted if at least one gpio pin is in event pending state. the selection of the target means of system notification is determined by the gpevr register. if irq is selected as one of the means for the system notification, the specific irq line is determined by the irq selection procedure of the device configura- tion. the assertion of any means of system notification is blocked when the gpio functional block is deactivated. if the output of a gpio pin is enabled, it may be put in event pending state by the software when writing to the gpdo register. a pending edge event may be cleared by clearing the corresponding gpevst bit. however, a level event source may not be released by software (except for disabling the source) as long as the pin is in active level. when level event is used, it is recommended to disable the input debouncer. upon deactivation of the gpio port, the gpevst register is cleared and access to both the gpevst and gpeven registers is disabled. all system notification means including the target irq line are detached from the gpio and de-asserted. before enabling any system notification, it is recommended to set the desired event configuration and then verify that the status registers are cleared. 6.4 gpio port registers the register maps in this chapter use the following abbreviations for type: l r/w = read/write. l r = read from a speci?c address returns the value of a speci?c register. w rite to the same address is to a different register. l w = w rite. l ro = read only. l r/w1c = read/write 1 t o clear. w riting 1 t o a bit clears it to 0. writing 0 has no effect. event pending indicator smi irq event routing logic pwureq enable enable irq gpio pin event routing register bit 2 bit 1 bit 0 routed events from other gpio pins routing routingrouting pwureq enable smi
6.0 general-purpose input/output (gpio) port (continued) 133 www.national.com 6.4.1 gpio pin configuration (gpcfg) register this is a group of eight identical configuration registers, each of which is associated with one gpio pin. the entire set is mapped to the pnp configuration space. the mapping scheme is based on the gpsel register, which functions as an index register and the specific gpcfg register, which reflects the configuration of the currently selected pin. for details on the gpsel register, refer to the device architecture and configuration chapter. bits 4-6 are applicable only for the enhanced gpio port with event detection support. in the basic port, these bits are re- served, return 0 on read and have no effect on port functionality. location: device specific type: r/w (bit 3 is set only) bit 76543210 name reserved event de- bounce en- able event po- larity event type lock pull-up control output type output en- able reset 01000100 bit description 7 reserved. 6 event debounce enable. 0: disabled 1: enabled (default) 5 event polarity. this bit de?nes the polarity of the signal that causes a detection of an event from the corresponding gpio pin (falling/low o r rising/high). 0: falling edge or low-level input (default) 1: rising edge or high-level input 4 event type. this bit de?nes the signal type that causes a detection of an event from the corresponding gpio pin. 0: edge input (default) 1: level input 3 lock . this bit locks the corresponding gpio pin. once this bit is set to 1 by software, i t can only be cleared to 0 by system reset or power-off. pin multiplexing is functional until the multiplexing lock bit is 1. (refer to the device architecture and configuration chapter.) 0: no effect (default) 1: direction, output type, pull-up and output value locked 2 pull-up control . this bit is used to enable/disable the internal pull-up capability of the corresponding gpio pin. it supports open-drain output signals with internal pull-ups and ttl input signals. 0: disabled 1: enabled (default) 1 output type. this bit controls the output buffer type (open-drain or push-pull) of the corresponding gpio pin. 0: open-drain (default) 1: push-pull 0 output enable. this bit indicates the gpio pin output state. i t has no effect on input. 0: tri-state (default) 1: output enabled
6.0 general-purpose input/output (gpio) port (continued) 134 www.national.com 6.4.2 gpio pin event routing (gpevr) register this is a group of eight identical configuration registers, each of which is associated with one gpio pin. the entire set is mapped to the pnp configuration space. the mapping scheme is based on the gpsel register, which functions as an index register and the specific gper register, which reflects the routing configuration of the currently selected pin. for details on the gpsel register, refer to the device architecture and configuration chapter. this set of registers is applicable only for the enhanced gpio port with event detection support. in the basic port, this register set is reserved, returns 0 on read and has no effect on port functionality. location: device specific type: r/w 6.4.3 gpio port runtime register map bit 76543210 name reserved gpio event to pwureq enable gpio event to smi en- able gpio event to irq en- able reset 00000001 bit description 7-3 reserved. 2 gpio event to pwureq enable . this bit is used to enable/disable the routing of the corresponding gpio detected event to pwureq. 0: disabled (default) 1: enabled 1 gpio event to smi enable. this bit is used to enable/disable the routing of the corresponding gio detected event to smi. 0: disabled (default) 1: enabled 0 gpio event to irq enable. this bit is used to enable/disable the routing of the corresponding gpio detected event to irq. 0: disabled 1: enabled (default) offset mnemonic register name type section device speci?c 1 1. the location of this register is de?ned in the de vice architecture and con?gur ation chapter in section 2.15.1. gpdo gpio data out r/w 6.4.4 device speci?c 1 gpdi gpio data in ro 6.4.5 device speci?c 1 gpeven gpio event enable r/w 6.4.6 device speci?c 1 gpevst gpio event status r/w1c 6.4.7
6.0 general-purpose input/output (gpio) port (continued) 135 www.national.com 6.4.4 gpio data out register (gpdo) location: device specific type: r/w 6.4.5 gpio data in register (gpdi) location: device specific type: ro bit 76543210 name data out reset 11111111 bit description 7 data out. bits 7-0 correspond to pins 7-0, respectively. the value of each bit determines the value driven on the corresponding gpio pin when its output buffer is enabled. writing to the bit latches the written data unless the bit is locked by the gpcfg register lock bit. reading the bit returns its value regardless of the pin value and con?guration. 0: corresponding pin driven to low when output enabled 1: corresponding pin driven or released to high (according to buffer type and static pull-up selection) when output enabled 6 5 4 3 2 1 0 bit 76543210 name data in reset xxxxxxxx bit description 7 data in. bits 7-0 correspond to pins 7-0, respectively. reading each bit returns the value of the corresponding gpio pin regardless of the pin con?guration and the gpdo register value. w rite is ignored. 0: corresponding pin level l ow 1: corresponding pin level high 6 5 4 3 2 1 0
6.0 general-purpose input/output (gpio) port (continued) 136 www.national.com 6.4.6 gpio event enable register (gpeven) location: device specific type: r/w 6.4.7 gpio event status register (gpevst) location: device specific type: r/w1c bit 76543210 name event enable reset 00000000 bit description 7 event enable. bits 7-0 correspond to pins 7-0, respectively. each bit enables system noti?cation triggering by the corresponding gpio pin. the bit has no effect on the corresponding status bit in the gpevst register. 0: irq generation by corresponding gpio pin masked 1: irq generation by corresponding gpio pin enabled 6 5 4 3 2 1 0 bit 76543210 name status reset 00000000 bit description 7 status. bits 7-0 correspond to pins 7-0, respectively. each bit is an edge detector that is set to 1 by the hardware upon detection of an active edge (i.e. edge that matches the irq polarity bit) on the corresponding gpio pin. this edge detection is independent of the event type or the event enable bit in the gpeven register. however, the bit may re?ect the event status for enabled, edge-trigger event sources. w riting 1 t o the status bit clears it to 0. 0: no active edge detected since last cleared 1: active edge detected 6 5 4 3 2 1 0
137 www.national.com 7.0 watchdog timer (wdt) 7.1 overview the watchdog timer prompts the system via smi or interrupt when no system activity is detected on a predefined selec- tion of system events for a predefined period of time of between 1 and 255 minutes or seconds. the numeric value (1-255) is configured in the wdto register (wdto); the time unit used for counting down (minutes or seconds) is configured in the status register (wdst). the watchdog timer monitors four maskable system events: the interrupt request lines of the keyboard, mouse and the two serial ports (uart1 and uart2). the system prompt is performed by asserting a special-purpose output pin ( wdo), which can be attached to external smi. alternatively, this indication can be routed to any arbitrary irq line and is also avail- able on a status bit that can be read by the host. this chapter describes the generic watchdog timer functional block. a device may include a different implementation. for device specific implementation, see the de vice architecture and con?gur ation chapter. 7.2 functional description this section describes how the watchdog timer works. by default, the watchdog timer counts down in minutes. to change the time unit from minutes to seconds, reconfigure the wdst register as defined in section 7.4 on page 140. the watchdog timer consists of an 8-bit counter and three registers: timeout register (wdto), mask register (wdmsk) and status register (wdst). the counter is an 8-bit down counter that is clocked every minute or second and is used for the timeout period countdown. the wdto register holds the programmable timeout, which is the period of inactivity after which the watchdog timer prompts the system (1 to 255 minutes or seconds). the wdmsk register determines which system events are enabled as watchdog timer trigger events to restart the countdown. the wdst register holds the watchdog timer status bit that reflects the value of the wdo pin and indicates that the timeout period has expired. in addition, it sets the time unit (minutes or seconds). figure 21 shows the functionality of the watchdog timer. figure 21. watchdog timer functional diagram upon reset, the timeout register (wdto) is initialized to zero, the timer is deactivated, the wdo is inactive (high) and all trigger events are masked. upon writing to the wdto register, the timer is activated while the counter is loaded with the timeout value and starts count- ing down every minute or second. if a trigger event (unmasked system event) occurs before the counter has expired (reached zero), the counter is reloaded with the timeout period (from wdto register) and restarts the countdown. if no trig- ger event occurs before the timeout period expires, the counter reaches zero and stops counting. consequently, the wdo pin is asserted (pulled low) and the wdo status bit is cleared to 0. writing to the wdto register de-asserts the wdo output (released high) and sets the wdo status bit to 1. if a non-zero value is written, a new countdown starts as described above. if 00h is written, the timer is deactivated. to summarize, the wdo output is de-asserted (high) and the status bit is set to 1 (inactive) upon: l reset, or l activating the watchdog timer or l writing to the wdto register. the wdo output is asserted (low) and the wdo status is set to zero (active) when the counter reaches zero. when an irq is assigned to the watchdog timer (through the watchdog timer device configuration), the selected irq level is active as long as the wdo status bit is low (active). wdto register timer zero detector wdo interrupt wdmsk write load reload enable bits status bit data bus register serial port 2 irq serial port 1 irq mouse irq keyboard irq 0123 1 minute/second clock
7.0 watchdog timer (wdt) (continued) 138 www.national.com 7.3 watchdog timer registers the watchdog timer registers, at offsets 00h-02h relative to the watchdog base address, are shown in the following register map. the base address is defined by designated registers in the watchdog timer device configuration register set. the following abbreviations are used to indicate the register type: ? r/w = read/write. ? r = read from a speci?c address returns the value of a speci?c register. w rite to the same address is to a different register. ? w = w rite. ? ro = read only, ? r/w1c = read/write 1 t o clear. w riting 1 t o a bit clears it to 0. writing 0 has no effect. 7.3.1 watchdog timer register map 7.3.2 watchdog timeout register (wdto) this register holds the programmable timeout period, which is between 1 and 255 minutes or seconds. writing to this register de-asserts the wdo output and sets the wdo status bit to 1 (inactive). additionally, writing to this register is interpreted as a command for starting or stopping the watchdog timer, according to the data written. if a non-zero value is written, the timer is activated (countdown starts). if a non-zero value is written when the counter is running, the timer is immediately reloaded with the new value and starts counting down from the new value. if 00h is written, the timer and its outputs are de- activated. location: offset 00h type: r/w offset mnemonic register name type section 00h wdto watchdog timeout r/w 7.3.2 01h wdmsk watchdog mask r/w 7.3.3 02h wdst watchdog status ro 7.3.4 03h reserved bit 76543210 name programmed timeout period reset 00000000 bit description 7-0 programmed timeout period. these bits hold the binary value of the timeout period in minutes or seconds (1 to 255). a value of 00h halts the counter and forces the outputs to inactive l evels. a d evice reset clears the register to 00h. 00h: timer and wdo outputs inactive 01h-ffh: programmed timeout period (in minutes or seconds)
7.0 watchdog timer (wdt) (continued) 139 www.national.com 7.3.3 watchdog mask register (wdmsk) this register is used to determine which system events (irq) are enabled as watchdog timer trigger events. an enabled irq event becomes a trigger event that causes the timer to reload the wdto and restart the countdown. this register enables or masks the trigger events that restart the watchdog timer. location: offset 01h type: r/w bit 7654 3 2 10 name reserved serial port 2 irq trigger enable serial port 1 irq trigger enable mouse irq trigger enable kbd irq trigger enable reset 0000 0 0 00 bit description 7-4 reserved. 3 serial port 2 irq trigger enable. this bit enables the irq assigned to serial port 2 t o t rigger watchdog timer reloading. 0: serial port 2 irq not a t rigger event 1: an active serial port 2 irq enabled as a trigger event 2 serial port 1 irq trigger enable. this bit enables the irq assigned to serial port 1 t o t rigger watchdog timer reloading. 0: serial port 1 irq not a t rigger event 1: an active serial port 1 irq enabled as a trigger event 1 mouse irq trigger enable. this bit enables the irq assigned to the mouse to trigger watchdog timer reloading. 0: mouse irq not a t rigger event 1: an active mouse irq enabled as a trigger event 0 kbd irq trigger enable. this bit enables the irq assigned to the keyboard to trigger reloading of the watchdog timer. 0: keyboard irq not a t rigger event 1: an active keyboard irq enabled as a trigger event
7.0 watchdog timer (wdt) (continued) 140 www.national.com 7.3.4 watchdog status register (wdst) this register holds the watchdog timer status, which reflects the value of the wdo pin and indicates that the timeout period has expired. on reset or on watchdog timer activation, this register is initialized to 01h. location: offset 02h type: ro 7.4 counting down in seconds to select seconds (instead of minutes) as the time unit used by the watchdog timer to countdown: 1. in the wdst register (see section 7.3.4), write 80h to set bit 7 to 1. 2. in the wdst register, write 84h to set bit 2 to 1. 3. in the wdto register (see section section 7.3.2), set the number of seconds to countdown (in hexadecimal notation, for example, 0a is 10 seconds, ff is 255 seconds). 7.5 watchdog timer register bitmap bit 76543210 name time unit reserved time unit reserved wdo value reset 00000001 bit description 7 time unit. 0: minutes (default) 1: seconds (see section 7.4) 6-3 reserved. 2 time unit. 0: minutes (default) 1: seconds (see section 7.4) 1 reserved. 0 wdo value. this bit re?ects the value of the wdo signal (even if wdo is not configured for output). 0: wdo active 1: wdo inactive (default) register bits offset mnemonic 7 6 5 4 3 2 1 0 00h wdto programmed timeout period 01h wdmsk reserved serial port 2 irq trigger enable serial port 1 irq trigger enable mouse irq trigger enable kbd irq trigger enable 02h wdst time unit reserved time unit reserved wdo value
141 www.national.com 8.0 access.bus interface (acb) the acb is a two-wire synchronous serial interface compatible with the access.bus physical layer. the acb is also com- patible with intel's smbus and philips i 2 c. the acb can be configured as a bus master or slave and can maintain bi-direc- tional communication with both multiple master and slave devices. as a slave device, the acb may issue a request to become the bus master. the acb allows easy interfacing to a wide range of low-cost memories and i/o devices, including eeproms, srams, tim- ers, adc, dac, clock chips and peripheral drivers. this chapter describes the general acb functional block. a device may include a different implementation. for device spe- cific implementation, see the de vice architecture and con?gur ation chapter. 8.1 overview the access.bus protocol uses a two-wire interface for bi-directional communication between the devices connected to the bus. the two interface lines are the serial data line (sdl) and the serial clock line (scl). these lines should be connected to a positive supply via an internal or external pull-up resistor and should remain high even when the bus is idle. each ic has a unique address and can operate as a transmitter or a receiver (though some peripherals are only receivers). during data transactions, the master device initiates the transaction, generates the clock signal and terminates the transac- tion. for example, when the acb initiates a data transaction with an attached access.bus compliant peripheral, the acb becomes the master. when the peripheral responds and transmits data to the acb, their master/slave (data transaction ini- tiator and clock generator) relationship is unchanged, even though their transmitter/receiver functions are reversed. 8.2 functional description 8.2.1 data transactions one data bit is transferred during each clock pulse. data is sampled during the high state of the serial clock (scl). conse- quently, throughout the clocks high period, the data should remain stable (see figure 22). any changes on the sda line during the high state of the scl and in the middle of a transaction aborts the current transaction. new data should be sent during the low scl state. this protocol permits a single data line to transfer both command/control information and data, using the synchronous serial clock. each data transaction is composed of a start condition, a number of byte transfers (set by the software) and a stop condi- tion to terminate the transaction. each byte is transferred with the most significant bit first. after each byte (8 bits), an ac- knowledge signal must follow. the following sections provide further details of this process. during each clock cycle, the slave can stall the master while it handles the received data or prepares new data. this can be done for each bit transferred, or on a byte boundary, by the slave holding scl low to extend the clock-low period. typically, slaves extend the first clock cycle of a transfer if a byte read has not yet been stored or if the next byte to be transmitted is not yet ready. some microcontrollers with limited hardware support for access.bus extend the access after each bit, thus allowing the software to handle this bit. 8.2.2 start and stop conditions the access.bus master generates start and stop conditions (control codes). after a start condition is generated, the bus is considered busy and retains this status for a certain time after a stop condition is generated. a high-to-low transition of the data line (sda) while the clock (scl) is high indicates a start condition. a low-to-high transition of the sda line while the scl is high indicates a stop condition (figure 23). after a stop condition is issued, the data in the received buffer is not valid. in addition to the first start condition, a repeated start condition can be generated in the middle of a transaction. this allows another device to be accessed or a change in the direction of data transfer. sda scl data line stable: data valid change of data allowed figure 22. bit transfer
8.0 access.bus interface (acb) (continued) 142 www.national.com 8.2.3 acknowledge (ack) cycle the ack cycle consists of two signals: the ack clock pulse sent by the master with each byte transferred and the ack signal sent by the receiving device (see figure 24). the master generates the ack clock pulse on the ninth clock pulse of the byte transfer. the transmitter releases the sda line (permits it to go high) to allow the receiver to send the ack signal. the receiver must pull down the sda line during the ack clock pulse, signalling that it has correctly received the last data byte and is ready to receive the next byte. figure 25 illustrates the ack cycle. sda scl s p start condition stop condition figure 23. start and stop conditions s p start condition stop condition sda scl msb ack ack 12 3 - 6 7 8 9 1 2 3 - 8 9 acknowledge signal from receiver byte complete interrupt within receiver clock line held low by receiver while interrupt is serviced figure 24. access.bus data transaction s start condition scl 12 3 - 6 7 8 9 transmitter stays off bus during acknowledge clock acknowledge signal from receiver data output by transmitter data output by receiver figure 25. access.bus acknowledge cycle
8.0 access.bus interface (acb) (continued) 143 www.national.com 8.2.4 acknowledge after every byte rule according to this rule, the master generates an acknowledge clock pulse after each byte transfer and the receiver sends an acknowledge signal after every byte received. there are two exceptions to this rule: ? when the master is the receiver, it must indicate to the transmitter the end of data by not acknowledging (negative ac- knowledge) the last byte clocked out of the slave. this negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the sda line is not pulled down. ? when the receiver is full or otherwise occupied or if a problem has occurred, the receiver sends a negative acknowledge to indicate that it cannot accept additional data bytes. 8.2.5 addressing transfer formats each device on the bus has a unique address. before any data is transmitted, the master transmits the address of the slave being addressed. the slave device should send an acknowledge signal on the sda line once it recognizes its address. the address consists of the first seven bits after a start condition. the direction of the data transfer (r/ w) depends on the bit sent after the address, the eighth bit. a low-to-high transition during a scl high period indicates the stop condition and ends the transaction of sda (see figure 26). when the address is sent, each device in the system compares this address with its own. if there is a match, the device considers itself addressed and sends an acknowledge signal. depending on the state of the r/ w bit (1=read, 0=write), the device acts either as a transmitter or a receiver. the i 2 c bus protocol allows a general call address to be sent to all slaves connected to the bus. the first byte sent specifies the general call address (00h). the second byte specifies the meaning of the general call (for example, write slave address by software only). those slaves that require data acknowledge the call and become slave receivers; other slaves ignore the call. 8.2.6 arbitration on the bus multiple master devices on the bus require arbitration between their conflicting bus access demands. control of the bus is initially determined according to address bits and clock cycle. if the masters are trying to address the same slave, data com- parisons determine the outcome of this arbitration. in master mode, the device immediately aborts a transaction if the value sampled on the sda line differs from the value driven by the device. (an exception to this rule is sda while receiving data. the lines may be driven low by the slave without causing an abort.) the scl signal is monitored for clock synchronization and to allow the slave to stall the bus. the actual clock period is set by the master with the longest clock period or by the slave stall period. the clock high period is determined by the master with the shortest clock high period. when an abort occurs during the address transmission, a master that identifies the conflict should give up the bus, switch to slave mode and continue to sample sda to check if it is being addressed by the winning master on the bus. s p start condition stop condition sda scl 1 - 7 8 9 1 - 7 8 9 1 - 7 8 9 address r/ w ack data ack data ack figure 26. a complete access.bus data transaction
8.0 access.bus interface (acb) (continued) 144 www.national.com 8.2.7 master mode requesting bus mastership an access.bus transaction starts with a master device requesting bus mastership. it asserts a start condition followed by the address of the device it wants to access. if this transaction is successfully completed, the software may assume that the device has become the bus master. for the device to become the bus master, the software should perform the following steps: 1. configure the inten bit of the acbctl1 register to the desired operation mode (polling or interrupt) and set the start bit of this register. this causes the acb to issue a start condition on the access.bus when the access.bus becomes free (bb bit of the acbcst register is cleared or other conditions that can delay start). it then stalls the bus by holding scl low. 2. if a bus conflict is detected (i.e., another device pulls down the scl signal), the ber bit of the acbst register is set. 3. if there is no bus conflict, the master bit of the acbst register and the scast of the acbst register are set. 4. if the inten bit of the acbctl1 register is set and either the ber or sdast bit of the acbst register is set, an interrupt is issued. sending the address byte when the device is the active master of the access.bus (the master bit of the acbst register is set), it can send the address on the bus. the address sent should not be the devices own address, as defined by the addr bit of the acbaddr register if the saen bit of this register is set, nor should it be the global call address if the gcmtch bit of the acbcst register is set. to send the address byte, use the following sequence: 1. for a receive transaction where the software wants only one byte of data, set the acb bit of the acbctl1 register. if only an address needs to be sent or if the device requires stall for some other reason, set the stastre bit of the acbctl1 register. 2. write the address byte (7-bit target device address) and the direction bit to the acbsda register. this causes the acb to generate a transaction. at the end of this transaction, the acknowledge bit received is copied to the negack bit of the acbst register. during the transaction, the sda and scl lines are continuously checked for conflict with other de- vices. if a conflict is detected, the transaction is aborted, the ber bit of the acbst register is set and the master bit of this register is cleared. 3. if the stastre bit of the acbctl1 register is set and the transaction was successfully completed (i.e., both the ber and negack bits of the acbst register are cleared), the stastr bit is set. in this case, the acb stalls any further access.bus operations (i.e., holds scl low). if the inten bit of the acbctl1 register is set, it also sends an interrupt request to the host. 4. if the requested direction is transmit and the start transaction was completed successfully (i.e., neither the negack nor the ber bit of the acbst register is set and no other master has accessed the device), the sdast bit of the acbst register is set to indicate that the acb awaits attention. 5. if the requested direction is receive, the start transaction was completed successfully and the stastre bit of the acbctl1 register is cleared, the acb starts receiving the first byte automatically. 6. check that both the ber and negack bits of the acbst register are cleared. if the inten bit of the acbctl1 register is set, an interrupt is generated when either the ber or negack bit of the acbst register is set. master transmit after becoming the bus master, the device can start transmitting data on the access.bus. to transmit a byte in an interrupt or polling controlled operation, the software should: 1. check that both the ber and negack bits of the acbst register are cleared and that the sdast bit of the acbst register is set. if the stastre bit of the acbctl1 register is set, also check that the stastr bit of the acbst register is cleared (and clear it if required). 2. write the data byte to be transmitted to the acbsda register. when either the negack or ber bit of the acbst register is set, an interrupt is generated. when the slave responds with a negative acknowledge, the negack bit of the acbst register is set and the sdast bit of the acbst register remains cleared. in this case, if the inten bit of the acbctl1 register is set, an interrupt is issued.
8.0 access.bus interface (acb) (continued) 145 www.national.com master receive after becoming the bus master, the device can start receiving data on the access.bus. to receive a byte in an interrupt or polling operation, the software should: 1. check that the sdast bit of the acbst register is set and that the ber bit is cleared. if the stastre bit of the acbctl1 register is set, also check that the stastre bit of the acbst register is cleared (and clear it if required). 2. set the ack bit of the acbctl1 register to 1, if the next byte is the last byte that should be read. this causes a negative acknowledge to be sent. 3. read the data byte from the acbsda register. before receiving the last byte of data, set the ack bit of the acbctl1 register. master stop to end a transaction, set the stop bit of the acbctl1 register before clearing the current stall flag (i.e., the sdast, negack or stastr bit of the acbst register). this causes the acb to send a stop condition immediately and to clear the stop bit of the acbctl1 register. a stop condition may be issued only when the device is the active bus master (the master bit of the acbst register is set). master bus stall the acb can stall the access.bus between transfers while waiting for the host response. the access.bus is stalled by holding the scl signal low after the acknowledge cycle. note that this is interpreted as the beginning of the following bus operation. the user must make sure that the next operation is prepared before the flag that causes the bus stall is cleared. the flags that can cause a bus stall in master mode are: l negative a cknowledge after sending a byte (negack bit of the acbst register = 1). l sdast bit of the acbst register = 1 . l stastre bit of the acbctl1 register = 1 after a successful start (stastr bit of the acbst register =1). repeated start a repeated start is performed when the device is already the bus master (master bit of the acbst register is set). in this case, the access.bus is stalled and the acb awaits host handling due to the following states in the acbst register: neg- ative acknowledge (negack bit = 1), empty buffer (sdast bit = 1) and/or a stall after start (stastr bit = 1). for a repeated start: 1. set the start bit of the acbctl1 register = 1. 2. in master receive mode, read the last data item from acbsda. 3. follow the address send sequence, as described in sending the address byte. 4. if the acb was awaiting handling (stastr bit of the acbst register = 1), clear it only after writing the requested address and direction to acbsda. master error detection the acb detects illegal start or stop conditions (i.e., a start or stop condition within the data transfer or the acknowledge cycle) and a conflict on the data lines of the access.bus. if an illegal condition is detected, ber is set and master mode is exited (master bit of the acbst. register is cleared). bus idle error recovery when a request to become the active bus master or a restart operation fails, the ber bit of the acbst register is set to indicate the error. in some cases, both the device and the other device may identify the failure and leave the bus idle. in this case, the start sequence may be incomplete and the access.bus may remain deadlocked. to recover from deadlock, use the following sequence: 1. clear the ber and bb bits of the acbcst register. 2. wait for a timeout period to check that there is no other active master on the bus (the bb bit remains cleared). 3. disable and re-enable the acb to put it in the non-addressed slave mode. this completely resets the functional block. at this point, some of the slaves may not identify the bus error. to recover, the acb becomes the bus master: it asserts a start condition, sends an address byte and then asserts a stop condition that synchronizes all the slaves.
8.0 access.bus interface (acb) (continued) 146 www.national.com 8.2.8 slave mode a slave device waits in idle mode for a master to initiate a bus transaction. whenever the acb is enabled and is not acting as a master (the master bit of the acbst register is cleared), it acts as a slave device. once a start condition on the bus is detected, the device checks whether the address sent by the current master matches either: l the addr bit value of the acbaddr register, i f the saen bit = 1 , o r l the general call address if the gcmen bit of the acbctl1 register = 1 . this match is checked even when the master bit is set. if a bus conflict (on sda or scl) is detected, the ber bit of the acbst register is set, the master bit is cleared and the device continues to search the received message for a match. if an address match or a global match is detected: 1. the device asserts its sda pin during the acknowledge cycle. 2. the match bit of the acbcst register and the nmatch bit of the acbst register are set. if the xmit bit of the acbst register is set (slave transmit mode), the sdast bit of the acbst register is set to indicate that the buffer is empty. 3. if the inten bit of the acbctl1 register is set, an interrupt is generated the nminte bit is also set. 4. the software then reads the xmit bit of the acbst register to identify the direction requested by the master device. it clears the nmatch bit of the acbst register so future byte transfers are identified as data bytes. slave receive and transmit slave receive and transmit are performed after a match is detected and the data transfer direction is identified. after a byte transfer, the acb extends the acknowledge clock until the software reads or writes the acbsda register. the receive and transmit sequences are identical to those used in the master routine. slave bus stall when operating as a slave, the device stalls the access.bus by extending the first clock cycle of a transaction in the fol- lowing cases: l sdast bit of the acbst register is set. l nmatch bit of the acbst register and nminte bit of the acbctl1 register are set. slave error detection the acb detects illegal start and stop conditions on the access.bus (i.e., a start or stop condition within the data transfer or the acknowledge cycle). when this occurs, the ber bit is set and match and gmatch are cleared, setting the acb as an unaddressed slave. 8.2.9 configuration sda and scl signals the sda and scl are open-drain signals. the device permits the user to define whether to enable or disable the internal pull-up of each of these signals. acb clock frequency the acb permits the user to set the clock frequency for the access.bus clock. the clock is set by the sclfrq field of the acbctl2 register, which determines the scl clock period used by the device. this clock low period may be extended by stall periods initiated by the acb or by another access.bus device. in case of a conflict with another bus master, a shorter clock high period may be forced by the other bus master until the conflict is resolved.
8.0 access.bus interface (acb) (continued) 147 www.national.com 8.3 acb registers the following abbreviations are used to indicate the register type: ? r/w = read/write. ? r = read from a speci?c address returns the value of a speci?c register. w rite to the same address is to a different register. ? w = w rite. ? ro = read only. ? r/w1c = read/write 1 t o clear. w riting 1 t o a bit clears it to 0. writing 0 has no effect. 8.3.1 acb register map 8.3.2 acb serial data register (acbsda) this shift register is used to transmit and receive data. the most significant bit is transmitted (received) first and the least significant bit is transmitted (received) last. reading or writing to the acbsda register is allowed only when the sdast bit of the acbst register is set or for repeated starts after setting the start bit. an attempt to access this register under other conditions may produce unpredictable results. location: offset 00h type: r/w offset mnemonic register name type section 00h acbsda acb serial data r/w 8.3.2 01h acbst acb status varies per bit 8.3.3 02h acbcst acb control status varies per bit 8.3.4 03h acbctl1 acb control 1 r/w 8.3.5 04h acbaddr acb own address r/w 8.3.6 05h acbctl2 acb control 2 r/w 8.3.7 bit 76543210 name acb serial data reset
8.0 access.bus interface (acb) (continued) 148 www.national.com 8.3.3 acb status register (acbst) this register maintains the current acb status. on reset, and when the acb is disabled, acbst is cleared (00h). location: offset 01h type: varies per bit bit 76543210 name slvstp sdast ber negack stastr nmatch master xmit reset 00000000 bit type description 7 r/w1c slvstp (slave stop). writing 0 t o slvstp is ignored. 0: writing 1 o r acb disabled 1: stop condition detected after a slave transfer in which match or gcmatch was set 6ro sdast (sda status). 0: reading from the acbsda register during a receive o r when writing to it during a t ransmit. when acbctl1.start i s set, reading the acbsda register does not clear sdast. this enables acb t o send a repeated start i n master receive mode. 1: sda data register awaiting data (transmit - master or slave) o r holds data that should be read (receive - master or slave). 5 r/w1c ber (bus error). writing 0 t o ber is ignored. 0: writing 1 o r acb disabled 1: start o r stop condition detected during data transfer (i.e., start o r stop condition during the transfer of bits 2 through 8 and acknowledge cycle) or when an arbitration problem is detected. 4 r/w1c negack (negative acknowledge). writing 0 t o negack is ignored. 0: writing 1 o r acb disabled 1: transmission not acknowledged on the ninth clock (in this case, s dast is not set) 3 r/w1c stastr (stall after start). writing 0 t o s tastr is ignored. 0: writing 1 o r acb disabled 1: address sent successfully (i.e., a start condition sent without a bus error or negative a cknowledge), if acbctl1.stastre is set. this bit is ignored in slave mode. when stastr is set, it stalls the access.bus by pulling down the scl line and suspends any further action on the bus ( e.g., receive of ?rst byte in master receive mode). in addition, if acbctl1.inten is set, it also causes the acb to send an interrupt. 2 r/w1c nmatch (new match). writing 0 t o nmatch is ignored. if acbctl1.inten is set, an interrupt is sent when this bit is set. 0: software writes 1 t o this bit 1: address byte follows a start condition or a repeated start, causing a match or a global-call match. 1ro master. 0: arbitration loss (ber is set) or recognition of a stop condition 1: bus master request succeeded and master mode active 0ro xmit (transmit). direction bit. 0: master/slave transmit mode not active 1: master/slave transmit mode active
8.0 access.bus interface (acb) (continued) 149 www.national.com 8.3.4 acb control status register (acbcst) this register configures and controls the acb functional block. it maintains the current acb status and controls several acb functions. on reset and when the acb is disabled, the non-reserved bits of acbcst are cleared. location: offset 02h type: varies per bit bit 76543210 name reserved tgscl tsda gcmtch match bb busy reset 0 0 0 x 0000 bit type description 7-6 reserved. 5 r/w tgscl (toggle scl line). enables toggling the scl line during error recovery. 0: clock toggle completed 1: when the sda line is low, writing 1 t o this bit toggles the scl line for one cycle. w riting 1 t o tgscl while sda i s high is ignored 4ro tsda ( test sda line). this bit reads the current value of the sda line. i t can be used while recovering from an error condition in which the sda line is constantly pulled low by a n out-of-sync slave. data written to this bit is ignored. 3ro gcmtch (global call match). 0: start condition or repeated start and a stop condition (including illegal start o r stop condition) 1: in slave mode, acbctl1.gcmen is set and the address byte (the ?rst byte transferred after a start condition) is 00h 2ro match (address match). 0: start condition or repeated start and a stop condition (including illegal start o r stop condition) 1: acbaddr.saen is set and the ?rst seven bits of the address byte (the ?rst byte transferred after a start condition) match the 7-bit address in the acbaddr register 1 r/w1c bb (bus busy). 0: writing 1, acb disabled or stop condition detected 1: bus active ( a l ow level o n either sda o r scl) or start condition 0ro busy. this bit should always b e w ritten 0. this bit indicates the period between detecting a start condition and completing receipt of the address byte. after this, the acb i s either free or enters slave mode. 0: completion of any state below o r acb disabled 1: acb i s i n one of the following states: generating a start condition master mode (acbst.master is set) slave mode (acbcst.match or acbcst.gcmtch set)
8.0 access.bus interface (acb) (continued) 150 www.national.com 8.3.5 acb control register 1 (acbctl1) location: offset 03h type: r/w bit 76543210 name stastre nminte gcmen ack reserved inten stop start reset 00000000 bit description 7 stastre (stall after start enable). 0: when cleared, acbst.stastr can not be set. however, if acbst.stastr is set, clearing stastre will not clear acbst.stastr. 1: stall after start mechanism enabled; acb stalls the bus after the address byte 6 nminte (new match interrupt enable). 0: no interrupt issued on a n ew match 1: interrupt issued on a n ew match only if acbctl1.inten set 5 gcmen (global call match enable). 0: acb not responding to global call 1: global call match enabled 4 receive acknowledge . this bit is ignored in transmit mode. when the device acts as a receiver (slave or master), this bit holds the stop transmitting instruction that is transmitted during the next acknowledge cycle. 0: cleared after acknowledge cycle 1: negative a cknowledge issued on next received byte 3 reserved. 2 interrupt enable. 0: acb interrupt disabled 1: acb interrupt enabled. an interrupt is generated in response to one of the following events: detection of an address match (acbst.nmatch=1) and nminte=1 receipt of bus error (acbst.ber=1) receipt of negative acknowledge after sending a byte (acbst.negack=1) acknowledge of each transaction (same as the hardware set of the acbst.sdast bit) in master mode if acbctl1.stastre=1, after a successful start (acbst.stastr=1) detection of a stop condition while in slave mode (acbst.slvstp=1) 1 stop. 0: automatically cleared after stop issued 1: setting this bit in master mode generates a stop condition to complete or abort current message transfer 0 start. set this bit only when in master mode or when requesting master mode. 0: cleared after start condition sent or bus error (acbst.ber=1) detected 1: single or repeated start condition generated on the access.bus. i f the device is not the active master of the bus ( acbst.master=0), setting start generates a start condition when the access.bus becomes free (acbcst.bb=0). an address transmission sequence should then be performed. if the device is the active master of the bus ( acbst.master=1), setting start and then writing to the acbsda register generates a start condition. if a t ransmission is already in progress, a repeated start condition is generated. this condition can be used to switch the direction of the data ?ow between the master and the slave or to choose another slave device without separating them with a stop condition.
8.0 access.bus interface (acb) (continued) 151 www.national.com 8.3.6 acb own address register (acbaddr) this is a byte-wide register that holds the acb access.bus address. the reset value of this register is undefined. location: offset 04h type: r/w 8.3.7 acb control register 2 (acbctl2) this register enables/disables the functional block and determines the acb clock rate. location: offset 05h type: r/w bit 76543210 name saen addr reset bit description 7 saen (slave address enable). 0: acb does not check for an address match with addr field 1: addr field holds a valid address and enables the match of addr to an incoming address byte 6-0 addr (own address). these bits hold the 7-bit device address. when in slave mode, the ?rst seven bits received after a start condition are compared with this ?eld (the ?rst bit received is compared with bit 6 and the last bit with bit 0). if the address ?eld matches the received data and saen (bit 7) is 1, a match is declared. bit 7 6543210 name sclfrq enable reset 0 0000000 bit description 7-1 sclfrq (scl frequency). this ?eld de?nes the scl period (low and high time) when the device serves a s a bus master. the clock l ow and high times are de?ned as follows: t scll =t sclh = 2*sclfrq*t clk where t clk is the module input clock cycle, a s de?ned in the de vice architecture and con?gur ation chapter. sclfrq can be programmed to values in the range of 0001000 2 (8 10 ) through 1111111 2 (127 10 ). using any other value has unpredictable results. 0 enable. 0: acb disabled, acbctl1, acbst and acbcst cleared and clocks halted 1: acb enabled
8.0 access.bus interface (acb) (continued) 152 www.national.com 8.4 acb register bitmap register bits offset mnemonic 76543210 00h acbsda acb serial data 01h acbst slvstp sdast ber negack stastr nmatch master xmit 02h acbcst reserved tgscl tsda gcmtch match bb busy 03h acbctl1 stastre nminte gcmen ack reserved inten stop start 04h acbaddr saen addr 05h acbctl2 sclfrq enable
153 www.national.com 9.0 game port (gmp) 9.1 overview this chapter describes a generic game port. for the implementation used in this device, see the de vice architecture and con?gur ation chapter. the game port monitors the interface of up to two game devices and provides data that can be used to determine the exact momentary status of these game devices. a game device is an instrument used for giving commands to a pc, usually to control a game executed on that pc. a joystick is a commonly used game device. these commands are given by the game device in a passive manner by indicating several status parameters that can be captured by the system via the game port. the status of a game device includes the following parameters: l button status (pressed/released) of up to two buttons per game device. l horizontal (x-axis) position indicated by the game device. l vertical (y-axis) position indicated by the game device. figure 27 shows the basic system configuration of the game port. figure 27. game port system con?guration 9.2 functional description 9.2.1 game device axis position indication a typical game device has the following interface pins: l an x-axis position indicator. l a y-axis position indicator. l one or two button status indicator(s). the x and y axis indicators are fed into the game port via pins joynx and joyny, respectively, where n indicates the game device number. the status indicators of buttons 0 and 1 are fed into the game port via joynbtn0,1, respectively. the x and y axis position indication mechanism of each game device includes external components, as seen in figure 28. such a mechanism is implemented per game device axis line. figure 28. game device axis position indication mechanism game port game device game device interface x-axis y-axis button 1 button 0 game device game device a circuitry x-axis y-axis button 1 button 0 r cx r vx c x game port joynx joyny game device x/y-axis varying waveform shaping circuit pins resistor x/y-axis circuit discharge control x/y-axis indicators input path
9.0 game port (gmp) (continued) 154 www.national.com the varying resistors r vx and r vy are usually implemented in the game device. their resistance values are determined directly by the horizontal and vertical positions, respectively, indicated by the game device. the waveform shaping circuits are usually implemented outside the game device using constant resistors (r cx/y ) and constant capacitors (c x/y ). together with r vx/y , these components implement two r-c structures whose varying parameters are used to determine the exact momentary position indicated by the game device. when the game port is enabled and not in the midst of a game device position reading process, it drives the joynx,y pins low. in this state, the capacitors c x/y are completely discharged. 9.2.2 capturing the position the process of capturing the position indicated by the game device is initiated by a command given to the game port to release the joynx,y lines, thus allowing the capacitors c x/y to be charged. this command is given by performing a write access to offset 1 from the game port base address, which is the offset of the game port legacy status register (gmplst, see section 9.3.3). once joynx,y pins are released, r cx/y and r vx/y start charging c x/y , and the voltage level of the joynx,y pins increases until it reaches v ih . this process is described in figure 29. figure 29. position reading process waveform (not drawn to scale) the vertical and horizontal positions indicated by the game device are determined by measuring the time it takes for the voltage level on the joynx,y pins to reach the level of logic 1. since the charging time is determined by the resistance val- ues of r vx/y , measuring this time actually indicates the resistance values of r vx/y and therefore also reflects the position indicated by the game device. once an axis pin is sensed as logic 1, the axis circuit discharge control is activated in order to discharge c x/y . this causes the corresponding axis pin to be driven low for approximately 1.5 m sec. after that, this axis line is held low until another po- sition reading process is initiated. during the charge time and the 1.5 m sec discharge time that follows, the corresponding axis line does not respond to any reading process initiation. this prevents software from disturbing the position reading process and makes the position read- ing processes of all axis lines independent of each other. 9.2.3 button status indication the button status indication mechanism is described in figure 30. although this figure shows an active-low button (r bu0 >>r bd0 ), the polarity of the button can be either high or low, assuming that the game port software is aware of the buttons polarity. figure 30. game device button status indication mechanism time v cx/y [v] v dd 0 v ih time measured as position indication dischargecharge idle idle drive low release drive low rbu0 game port joynbtn0 joynbtn1 game device button status circuit pins buttons 0,1 status indicators input path rbd0
9.0 game port (gmp) (continued) 155 www.national.com a simple push-button mechanism is usually used to implement the game device buttons. the status of each button is sensed by the game port via the joynbtn0,1 pins as either high or low and is reflected by the gmplst register. it is the respon- sibility of the software to determine the actual status of the buttons according to their polarity, which depends on the specific implementation of the system and the game device. 9.2.4 operation modes the game port can be used to monitor the position and button status indicators in one of the following operation modes: l legacy mode. l enhanced mode. legacy mode legacy mode is enabled when bit 0 of the gmpctl register is set to 0, which is its default state. in this mode, the game device indicators are monitored by polling their momentary status via the game port legacy status register (gmplst, see section 9.3.3). the process of reading the position status of the game device(s) is initiated by performing a write access to offset 1 i n the game port address space. this write access causes the game port to release the joynx,y pins. when a joynx,y pin is released, the corresponding bit in the gmplst register is set to 1. to capture the position indicated by the game device, the software must poll the gmplst register and measure the time it takes for joynx,y to go high. this measurement should be performed by measuring the time during which an axis bit is 1. reading the status of the buttons of the game device is done by polling the gmplst register and looking for changes in the bits reflecting the status of the joynbtn0,1 pins. no debounce of the input signals is performed by the game port in legacy mode. it is the responsibility of the software to implement such debounce, if necessary. enhanced mode enhanced mode is enabled when bit 0 of the gmpctl register is set to 1. in enhanced mode, the game port hardware monitors the status indicators of the game device(s) and provides processed data that can be easily used by software to determine the complete status of the game device. the process of reading the position status of the game device(s) is initiated the same way it is done in legacy mode. how- ever, in enhanced mode, the game port hardware measures the c x/y charging time using four 16-bit up-counters. each one of the four axis status lines (two lines per game device) has a dedicated counter. once the game port releases the joynx,y to go high, each one of the counters starts counting until its associated axis status line reaches the voltage level of logic 1.
9.0 game port (gmp) (continued) 156 www.national.com when a position counter of a game device stops counting, its associated position counter ready bit in the gmpxst register is set. all the software has to do in this case is wait until the counters associated with the game device are ready and then read their values. the least significant byte of a position counter should be read first. the full 16-bit count value should be calculated as follows: x/y position count = gmpnx/yl + (gmpnx /yh * 256) where: gmpnx/yl indicates the low byte of the position counter of device n (either x or y axis) and gmpny/hl indicates the high byte of the position counter of device n (either x or y axis). it is the responsibility of the software to calibrate itself according to the actual count values acquired when the game device was set to indicate its extreme horizontal and vertical positions. if a position counter has reached the full count of ffffh, it means that this counter has overflowed. overflow means that the counter has reached its full count before the corresponding axis indicator has reached the level of logic 1. in such a case, the software must decide what to do. the game port supports the following clock frequencies for operating the position counters: l 1 mhz clock (default). l 500 khz clock. the clock frequency for the position counter of each game device is configured via the gmpctl register and should be set by the software to match the physical components of the external game device interface circuitry. setting the desired position counter frequency should be done before initiating a position status reading process. reading the status of the buttons of the game device(s) is done the same way it is done in legacy mode. in addition, an optional debouncer of 16 msec is implemented on each button status input. the debouncers are disabled by default and may be enabled by software via the gmpctl register. 9.2.5 operation control when the game port is operated in legacy mode, it can only be operated by polling (see section 9.2.4, legacy mode ). when the game port is operated in enhanced mode, both kinds of status reading operations (position and button) can be performed using polling or interrupt controlled operation. if polling controlled operation is preferred, the software should poll either the gmplst register for the direct status of the buttons as in legacy mode or the gmpxst register, which provides indications regarding button events detected by hard- ware. the gmpxst register should also be polled for the status of the position counters. when the status is ready, the counter values can be read. these values reflect the positions indicated by the game device. if interrupt controlled operation is preferred, the software should first define the events on which an interrupt request is to be issued. this is done by writing the required values to the gmpepol (see section 9.3.14) and gmpien (see section 9.3.5) registers. the gmpepol register defines the events on which the buttons cause an interrupt request to be issued. these events are all edge-triggered. the gmpien register determines which events are physically routed to the interrupt request assigned to the game port. an independent interrupt enable bit is implemented in the gmpien register for each one of the four buttons and two position counters of the two supported game devices.
9.0 game port (gmp) (continued) 157 www.national.com 9.3 game port registers the following abbreviations are used to indicate the register type: l r/w = read/write. l r = read from a speci?c address returns the value of a speci?c register. w rite to the same address is to a different register. l w = w rite. l ro = read only. l r/w1c = read/write 1 t o clear. w riting 1 t o a bit clears it to 0. writing 0 has no effect. 9.3.1 game port register map the following table lists the game port registers. for the game port register bitmap, see section 9.4. offset mnemonic register name type section 00h gmpctl game port control r/w 9.3.2 01h gmplst game port legacy status ro 9.3.3 02h gmpxst game port extended status r/w1c 9.3.4 03h gmpien game port interrupt enable r/w 9.3.5 04h gmpaxl game device a x position low byte ro 9.3.6 05h gmpaxh game device a x position high byte ro 9.3.7 06h gmpayl game device a y position low byte ro 9.3.8 07h gmpayh game device a y position high byte ro 9.3.9 08h gmpbxl game device b x position low byte ro 9.3.10 09h gmpbxh game device b x position high byte ro 9.3.11 0ah gmpbyl game device b y position low byte ro 9.3.12 0bh gmpbyh game device b y position high byte ro 9.3.13 0ch gmpepol game port event polarity r/w 9.3.14
9.0 game port (gmp) (continued) 158 www.national.com 9.3.2 game port control register (gmpctl) this register affects the functionality of the game port only when operated in enhanced mode (bit 0 o f this register is set to 1). bits 1,2 and 4-7 affect game port functionality, as described in the table below. location: offset 00h type: r/w bit 76543210 name device b button 1 debounce enable device b button 0 debounce enable device a button 1 debounce enable device a button 0 debounce enable reserved device b pre-scale enable device a pre-scale enable gmp enhanced mode enable reset 00000000 required 0 bit description 7 device b button 1 debounce enable. when set to 1, enables a 1 6 m s input debouncer on device b button 1 status input. 0: disabled (default) 1: enabled 6 device b button 0 debounce enable. same as bit 7 but for d evice b button 0. 0: disabled (default) 1: enabled 5 device a button 1 debounce enable. same as bit 7 but for d evice a button 1. 0: disabled (default) 1: enabled 4 device a button 0 debounce enable. same as bit 7 but for d evice a button 0. 0: disabled (default) 1: enabled 3 reserved. 2 device b pre-scale enable. this bit determines the clock frequency used by device b position counters. 0: 1 mhz (default) 1: 500 khz 1 device a pre-scale enable. this bit determines the clock frequency used by device a position counters. 0: 1 mhz (default) 1: 500 khz 0 gmp enhanced mode enable. 0: disabled (default) 1: enabled
9.0 game port (gmp) (continued) 159 www.national.com 9.3.3 game port legacy status register (gmplst) this register is functional in all game port operation modes. reading this register returns the status and the state of device a and b button and axis pins, as defined in the table below. writing to the offset of this register initiates a game device po- sition reading process by forcing a low pulse to be driven on the axis pins in legacy and enhanced modes and by initializing all position counters in enhanced mode. location: offset 01h type: ro bit 76543210 name device b button 1 pin status device b button 0 pin status device a button 1 pin status device a button 0 pin status device b y-axis pin status device b x-axis pin status device a y-axis pin status device a x-axis pin status reset xxxxxxxx bit description 7 device b button 1 pin status. this bit directly re?ects the status of device b button 1 input pin. 0: low 1: high 6 device b button 0 pin status. this bit directly re?ects the status of device b button 0 input pin. 0: low 1: high 5 device a button 1 pin status. this bit directly re?ects the status of device a button 1 input pin. 0: low 1: high 4 device a button 0 pin status. this bit directly re?ects the status of device a button 0 input pin. 0: low 1: high 3 device b y-axis pin status. this bit re?ects the state of device b y-axis input pin. 0: joyby pin is released for charging 1: joyby pin is driven low 2 device b x-axis pin status. this bit re?ects the state of device b x-axis input pin. 0: joybx pin is released for charging 1: joybx pin is driven low 1 device a y-axis pin status. this bit re?ects the state of device a y-axis input pin. 0: joyay pin is released for charging 1: joyay pin is driven low 0 device a x-axis pin status. this bit re?ects the status of device a x-axis input pin. 0: joyax pin is released for charging 1: joyax pin is driven low
9.0 game port (gmp) (continued) 160 www.national.com 9.3.4 game port extended status register (gmpxst) this register indicates which of the corresponding game device interface events have occurred. writing 1 t o a bit clears it. reading a position counter clears the corresponding counter ready bit. writing 0 to a bit has no effect. this register is functional only in enhanced mode. location: offset 02h type: r/w1c bit 76543210 name device b button 1 event status device b button 0 event status device a button 1 event status device a button 0 event status device b y-position counter ready device b x-position counter ready device a y-position counter ready device a x-position counter ready reset 00000000 bit description 7 device b button 1 event status. when set to 1, indicates that a d evice b button 1 event has occurred. the event itself is de?ned by the gmpepol register, see section 9.3.14. 0: event not active (default) 1: event active 6 device b button 0 event status. when set to 1, indicates that a d evice b button 0 event has occurred. the event itself is de?ned by the gmpepol register, see section 9.3.14. 0: event not active (default) 1: event active 5 device a button 1 event status. when set to 1, indicates that a d evice a button 1 event has occurred. the event itself is de?ned by the gmpepol register, see section 9.3.14. 0: event not active (default) 1: event active 4 device a button 0 event status. when set to 1, indicates that a d evice a button 0 event has occurred. the event itself is de?ned by the gmpepol register, see section 9.3.14. 0: event not active (default) 1: event active 3 device b y-position counter ready. when set to 1, indicates that the value of the y-position counter of device b can now b e read. 0: event not active (default) 1: event active 2 device b x-position counter ready. when set to 1, indicates that value of the x-position counter of device b can now b e read. 0: event not active (default) 1: event active 1 device a x-position counter ready. when set to 1, indicates that the value of the y-position counter of device a can now b e read. 0: event not active (default) 1: event active 0 device a x-position counter ready. when set to 1, indicates that the value of the x-position counter of device a can now b e read. 0: event not active (default) 1: event active
9.0 game port (gmp) (continued) 161 www.national.com 9.3.5 game port interrupt enable register (gmpien) this register defines the conditions on which the game port asserts its interrupt request signal. this register is functional only in enhanced mode. location: offset 03h type: r/w bit 76543210 name device b button 1 irq enable device b button 0 irq enable device a button 1 irq enable device a button 0 irq enable reserved position irq event de?nition device b position irq enable device a position irq enable reset 00000000 bit description 7 device b button 1 irq enable. when set to 1, the game port issues an interrupt request in response to an event triggered by button 1 o f d evice b. when set to 0, button 1 o f d evice b cannot cause interrupt requests to be issued. 0: disabled (default) 1: enabled 6 device b button 0 irq enable. same as bit 7 o f this register but for device b button 0. 0: disabled (default) 1: enabled 5 device a button 1 irq enable. same as bit 7 o f this register but for device a button 1. 0: disabled (default) 1: enabled 4 device a button 0 irq enable. same as bit 7 o f this register but for device a button 0. 0: disabled (default) 1: enabled 3 reserved. 2 position irq event de?nition de?nes the event on which the position irq is asserted for both game devices. 0: both x-position counter and y-position counter are ready 1: either x-position counter or y-position counter is ready 1 device b position irq enable. when set to 1, the game port issues an interrupt request when the position reading of device b i s completed and the position counters can be read. when set to 0, no interrupt request is issued in response to any change in the status of device b position counters. 0: disabled (default) 1: enabled 0 device a position irq enable. same as bit 2 o f this register but for device a. 0: disabled (default) 1: enabled
9.0 game port (gmp) (continued) 162 www.national.com 9.3.6 game device a x-axis position low byte (gmpaxl) reading this register returns the value of the low byte of the x-axis position counter of game device a. before reading this register verify that bit 0 o f gmpxst (device a position counter ready) is set to 1. writing to the offset of this register is ignored. this register is functional only in enhanced mode. location: offset 04h type: ro 9.3.7 game device a x-axis position high byte (gmpaxh) reading this register returns the value of the high byte of the x-axis position counter of game device a. read this register after reading the gmpaxl register and verifying that bit 0 o f gmpxst (device a position counter ready) is set to 1. writing to the offset of this register is ignored. this register is functional only in enhanced mode. location: offset 05h type: ro 9.3.8 game device a y-axis position low byte (gmpayl) reading this register returns the value of the low byte of the y-axis position counter of game device a. before reading this register, verify that bit 1 o f gmpxst (device a position counter ready) is set to 1. writing to the offset of this register is ignored. this register is functional only in enhanced mode. location: offset 06h type: ro 9.3.9 game device a y-axis position high byte (gmpayh) reading this register returns the value of the high byte of the y-axis position counter of game device a. read this register after reading the gmpayl register and verifying that bit 1 o f gmpxst (device a position counter ready) is set to 1. writing to the offset of this register is ignored. this register is functional only in enhanced mode. location: offset 07h type: ro bit 76543210 name device a x-axis position counter low byte reset 00000000 bit 76543210 name device a x-axis position counter high byte reset 00000000 bit 76543210 name device a y-axis position counter low byte reset 00000000 bit 76543210 name device a y-axis position counter high byte reset 00000000
9.0 game port (gmp) (continued) 163 www.national.com 9.3.10 game device b x-axis position low byte (gmpbxl) reading this register returns the value of the low byte of the x-axis position counter of game device b. before reading this register, verify that bit 2 o f gmpxst (device b position counter ready) is set to 1. writing to the offset of this register is ignored. this register is functional only in enhanced mode. location: offset 08h type: ro 9.3.11 game device b x-axis position high byte (gmpbxh) reading this register returns the value of the high byte of the x-axis position counter of game device b. before reading this register, verify that bit 2 o f gmpxst (device b position counter ready) is set to 1. writing to the offset of this register is ignored. this register is functional only in enhanced mode. location: offset 09h type: ro 9.3.12 game device b y-axis position low byte (gmpbyl) reading this register returns the value of the low byte of the y-axis position counter of game device b. before reading this register, verify that bit 3 o f gmpxst (device b position counter ready) is set to 1. writing to the offset of this register is ignored. this register is functional only in enhanced mode. location:offset 0ah type: ro 9.3.13 game device b y-axis position high byte (gmpbyh) reading this register returns the value of the high byte of the y-axis position counter of game device b. before reading this register, verify that bit 3 o f gmpxst (device b position counter ready) is set to 1. writing to the offset of this register is ignored. this register is functional only in enhanced mode. location:offset 0bh type: ro bit 76543210 name device b x-axis position counter low byte reset 00000000 bit 76543210 name device b x-axis position counter high byte reset 00000000 bit 76543210 name device b y-axis position counter low byte reset 00000000 bit 76543210 name device b y-axis position counter high byte reset 00000000
9.0 game port (gmp) (continued) 164 www.national.com 9.3.14 game port event polarity register (gmpepol) this register defines the polarity of button events on which the game port issues an interrupt request. this register is functional only in enhanced mode. location: offset 0ch type: r/w bit 76543210 name device b button 1 event polarity device b button 0 event polarity device a button 1 event polarity device a button 0 event polarity reset 00000000 bit description 7-6 device b button 1 event polarity. this bit de?nes the event polarity on which device b button 1 issues an interrupt request. bits 7 6 number 0 0 none (default) 0 1 rising edge 1 0 falling edge 1 1 rising and falling edge 5-4 device b button 0 event polarity. same as bits 7-6 of this register but for device b button 0. bits 5 4 number 0 0 none (default) 0 1 rising edge 1 0 falling edge 1 1 rising and falling edge 3-2 device a button 1 event polarity. same as bits 7-6 of this register but for device a button 1. bits 3 2 number 0 0 none (default) 0 1 rising edge 1 0 falling edge 1 1 rising and falling edge 1-0 device a button 0 event polarity. same as bits 7-6 of this register but for device a button 0. bits 1 0 number 0 0 none (default) 0 1 rising edge 1 0 falling edge 1 1 rising and falling edge
9.0 game port (gmp) (continued) 165 www.national.com 9.4 game port bitmap register bits offset mnemonic 76543210 00h gmpctl device b button 1 debounce enable device b button 0 debounce enable device a button 1 debounce enable device a button 0 debounce enable reserved device b pre-scale enable device a pre-scale enable gmp enhanced mode enable 01h gmplst device b button 1 pin status device b button 0 pin status device a button 1 pin status device a button 0 pin status device b y-axis pin status device b x-axis pin status device a y-axis pin status device a x-axis pin status 02h gmpxst device b button 1 event status device b button 0 event status device a button 1 event status device a button 0 event status device b y-position counter ready device b x-position counter ready device a y-position counter ready device a x-position counter ready 03h gmpien device b button 1 irq enable device b button 0 irq enable device a button 1 irq enable device a button 0 irq enable reserved position irq event de?nition device b position irq enable device a position irq enable 04h gmpaxl device a x-axis position counter low byte 05h gmpaxh device a x-axis position counter high byte 06h gmpayl d evice a y-axis position counter low byte 07h gmpayh d evice a y-axis position counter high byte 08h gmpbxl device b x-axis position counter low byte 09h gmpbxh device b x-axis position counter high byte 0ah gmpbyl device b y-axis position counter low byte 0bh gmpbyh device b y-axis position counter high byte 0ch gmpepol device b button 1 event polarity device b button 0 event polarity device a button 1 event polarity device a button 0 event polarity
166 www.national.com 10.0 musical instrument digital interface (midi) port 10.1 overview this chapter describes a generic midi port. for the implementation used in this device, see the de vice architecture and con?gur ation chapter. the midi port is an asynchronous receiver/transmitter that uses a two-wire, bi-directional, relatively slow communication channel to transmit and receive data bytes to or from midi-compliant devices, according to a predefined communication pro- tocol. the midi port is compatible with mpu-401 uart mode. the midi port was originally defined to establish a standard interface between computers and digital musical instruments such as synthesizers and has become the de facto standard for this purpose. however, the midi is also commonly used for other purposes such as communicating with advanced game devices. the midi port serves as a communication pipe between software and a midi device. the software and the midi device must interpret the data they exchange and act accordingly. the midi port supports the following two feature types: l legacy (mpu-401). l enhanced. legacy. these include all features supported by mpu-401 uart mode. they can all be operated via the legacy i/o ad- dress space of two bytes, traditionally allocated for the midi port. enhanced. these features extend the capabilities of the midi port. they can only be operated if the midi is allocated with an address space of at least three bytes. the basic system configuration of the midi port consists of the port itself, a single pull-up resistor for the mdrx pin and a midi-compliant device. this system configuration is shown in figure 31. the purpose of the pull-up resistor is to make sure that the midi port senses an inactive (high) midi receive signal in the absence of a midi device. figure 31. midi system con?guration 10.2 functional description the midi port consists of five major functional blocks: l internal bus interface unit. l port control and status registers. l data buffers and fifos. l midi communication engine. l midi signals routing control logic. see figure 32 for a block diagram of the midi port. midi port midi transmit midi receive game device midi device midi receive midi transmit mdrx pin mdtx pin r
10.0 musical instrument digital interface (midi) port (continued) 167 www.national.com figure 32. midi port block diagram 10.2.1 internal bus interface unit the internal bus interface unit handles all read and write transactions between the host and the registers of the midi port. it also controls the midi port interrupt request logic (see section 10.2.8). 10.2.2 port control and status registers a control register (mcntl, see section 10.3.6) and a status register (mstat, see section 10.3.4) allow the user to control the operation of the midi and provide status information regarding its various functional units. a command register (mcom, see section 10.3.5) allows the user to control the operation mode of the midi port by serving as a port via which the host can issue commands to the midi. a midi port command is defined as a write access to the midi command register. the meaning of each command is determined by the data byte written during this write access. 10.2.3 data buffers and fifos the data buffers and fifos function as a mechanism for synchronizing between the internal bus interface unit and the midi communication engine. this synchronization allows each of these units to handle its own tasks without having to pause to send/receive data to/from the other unit. synchronization also bridges the gap in the data transfer rate between these two units. data transfer rate matching is done when the fifos of the midi port are enabled. it allows the midi port to interface a bus at a relatively high data transfer rate while maintaining communication with a midi device over a communi- cation channel that supports a relatively low data transfer rate. 10.2.4 midi communication engine the midi communication engine handles the serializing of outgoing data and the de-serializing of incoming data transferred between the midi port and the midi device. during transmit (serial data transfer from the midi port to the midi device), the communication engine receives data bytes from the output data buffer or fifo, serializes them into a stream of data bits and transmits them as a sequence of high and low pulses over the mdtx pin according to the midi communication protocol. during receive (serial data transfer from the midi device to the midi port), the communication engine receives a sequence of high and low pulses via the mdrx pin, converts them into a stream of data bits and de-serializes them into data bytes that it sends to the input data buffer or fifo. both transmit and receive are performed at a fixed serial data rate of 31.25 kbits per second. the serial data format is also fixed and consists of one start bit, eight data bits and one stop bit. see the waveform illustrating a midi byte transfer in figure 33. internal interface midi routing control signals midi communication engine data buffers and fifos mdtx pin mdrx pin midi transmit signal midi receive signal (data serializer) 8 8 bus control tx data rx data superi/o internal bus midi port control and status registers read/write interface routing control data buffer status and control communication status and control asynchronous synchronous interfaceinterface unit 8 8 control tx data rx data
10.0 musical instrument digital interface (midi) port (continued) 168 www.national.com figure 33. midi byte transfer waveform 10.2.5 midi signals routing control logic the midi signals routing control logic controls the various routing options available for the midi transmit and receive sig- nals. it is controlled by the midi control register (mcntl, see section 10.3.6). these routing options are not part of the legacy definition of the midi port. 10.2.6 operation modes the midi port can be operated in one of the following modes: l pass-thru (non-uart) mode (default). l uart mode. pass-thru (non-uart) mode after a hardware reset, the midi port is in pass-thru mode. in this mode, transmission is disabled by default, and all writes to the midi data out register (mdo, see section 10.3.3) are ignored. transmission in this mode may be enabled by setting bit 4 o f the midi control register (mcntl, see section 10.3.6). receive in pass-thru mode is enabled and a 16-byte receive fifo is available. reading the midi data in register (mdi, see section 10.3.2) in this mode returns the oldest data stored in the receive fifo. if serial data is received while the re- ceive fifo is full with data that has not yet been read, the last received data is lost, thus maintaining the data that was pre- viously stored in the receive buffer. when in pass-thru mode, the midi port responds to commands issued by the host, as follows: l 3fh puts the midi port in uart mode. also, i n response to this command, the midi port puts an acknowledge byte of feh in the receive buffer. l a0h-a7h or abh causes the midi port to put an acknowledge byte of feh, followed by a data byte of 00h, in the re- ceive buffer. l ach causes the midi port to put an acknowledge byte of feh, followed by a data byte of 15h, in the receive buffer. l adh causes the midi port to put an acknowledge byte of feh, followed by a data byte of 01h, in the receive buffer. l afh causes the midi port to put an acknowledge byte of feh, followed by a data byte of 64h, in the receive buffer. l ffh resets the midi port to its initial state, including all the bits of the mstat register. i n response, the midi port puts an acknowledge of feh in the receive buffer. this command is usually referred to as the midi reset command. l the midi port responds to all other commands by putting an acknowledge byte of feh in the receive buffer. putting the acknowledge byte of feh is equivalent to receiving a data byte. therefore, once an acknowledge byte is put in the receive buffer, it causes the receive buffer empty status flag (see section 10.2.7) to be cleared, which may also cause a midi port interrupt request to be issued. when the receive fifo is disabled, switching from pass-thru mode to uart mode causes data stored in the receive buff- er to be lost. after switching to uart mode, the midi port is blocked for receive until the acknowledge byte is read from the receive buffer. if a command is issued to the midi port while the midi communication engine is in the middle of a byte transfer (the start bit has been transmitted or received), the execution of the command and the response are postponed until the ongoing byte transfer is completed. after each midi port operation in pass-thru mode, the midi status register (mstat, see section 10.3.4) is updated accord- ingly. midi signal data bits 10101010 start bit stop bit 32 m sec lsb msb
10.0 musical instrument digital interface (midi) port (continued) 169 www.national.com uart mode entering uart mode is done by software giving the midi port command of 3fh. once in uart mode, both transmit and receive are enabled. in addition, the two 16-byte receive and transmit fifos are automatically enabled. in uart mode, data written to the mdo register is placed in the transmit fifo, from which it is taken by the midi commu- nication engine and transmitted via the mdtx pin to the midi device. likewise, whenever the transmit fifo is not empty, the next byte is taken out by the communication engine and transmitted via the mdtx pin to the midi device. whenever serial data is received by the communication engine via the mdrx pin, it is de-serialized and put in the receive fifo. reading the mdi register returns the next byte in the receive fifo. the mdi register should not be read while the receive fifo is empty. if serial data is received while the receive fifo is full, this data is lost and not stored in the receive fifo, thus keeping the data that was previously stored in the receive fifo. when in uart mode, the midi port responds to commands given by the host as follows: l a command of ffh returns the midi port to pass-thru mode and resets it to its initial state. l all other commands issued while the midi port is in uart mode are ignored. when switching from uart mode to pass-thru mode, any data previously stored in the receive fifo is lost unless the fifo is enabled for pass-thru mode. as in pass-thru mode, if a command is issued to the midi port while the midi communication engine is in the middle of a byte transfer, the execution of the command and the response are postponed until the ongoing byte transfer is completed. the midi commands supported by the midi port and their respective responses are listed in table 50. after each midi port operation in uart mode, the mstat register is updated accordingly. table 50. midi commands supported by the midi port 10.2.7 midi port status flags the status of the various functional units of the midi port is reflected by the mstat register. this register is functional in both pass-thru and uart modes. some of the status indications provided by the mstat register are not included in the legacy definition of the midi port. these indications can be ignored if not required by the software. the following status flags are included in the legacy definition of the midi port: l receive buffer empty. l transmit buffer full. the receive buffer empty flag is reflected by bit 7 o f the mstat register. the transmit buffer full flag is reflected by bit 6 of the mstat register. when operating in uart mode, these bits reflect the status of the receive and transmit fifos. the receive buffer empty status flag is also cleared to 0 when an acknowledge byte is put by the midi port itself following a midi command. command midi port response pass-thru mode uart mode 3fh enter uart mode feh (acknowledge) ignored a0h-a7h, abh feh (acknowledge) 00h ignored ach feh (acknowledge) 15h ignored adh feh (acknowledge) 01h ignored afh feh (acknowledge) 64h ignored ffh midi port reset feh (acknowledge) enter pass-thru mode midi port reset others feh (acknowledge) ignored
10.0 musical instrument digital interface (midi) port (continued) 170 www.national.com the values of these bits are set by the midi port hardware and are not affected by reading the mstat register. the following status indications are provided by the midi port, although they are not included in the legacy definition of the midi port: l receive fifo full. l transmit fifo empty. l receive o verrun error. l midi port operation mode. the receive fifo full and transmit fifo empty status flags are reflected by mstat register bits 5 and 2, respectively. these bits are updated only when the midi port operates in uart mode or when in pass-thru mode with the receive fifo enabled. otherwise, these bits are constantly cleared. the values of these bits are set by the midi port hardware and are not affected by reading the mstat register. the receive overrun error flag indicates that serial data was received by the midi communication engine while the receive buffer of fifo was full. this flag is reflected by bit 3 o f the mstat register. it is updated in both pass-thru and uart modes. when a receive overrun event occurs, the data in the receive buffer/fifo is kept and all incoming data is lost. incoming data will keep getting lost until there is room in the receive buffer/fifo to accept it. the receive overrun error status flag is cleared when the mstat register is read. the midi port operation mode flag indicates whether the midi port currently operates in pass-thru or uart mode. this status flag is reflected by bit 4 o f the mstat register. it can be used by software to keep track of the currently selected midi port operation mode. 10.2.8 midi port interrupts the midi port supports interrupt assertion in both pass-thru and uart modes in response to one or both of the following events: l receive data ready. l transmit buffer empty. the receive data ready event refers to the case in which there is data to be read in the receive buffer/fifo. an interrupt request is asserted by the midi port to indicate a receive data ready event in one of the following cases: ? the midi port is in pass-thru mode, and the receive buffer contains a data or acknowledge byte that has not been read yet. in this case, the interrupt request is de-asserted once the receive buffer is read. ? the midi port is in uart mode and the receive fifo contains eight or more data bytes that have not been read yet, or it is in pass-thru mode with the receive fifo enabled. in this case, the interrupt request is de-asserted once the receive fifo level drops below eight bytes. ? either: the midi port is in uart mode, the receive fifo contains less than eight data bytes that have not been read yet, and no data was received by the communication engine, or the midi port is in pass-thru mode with the receive fifo enabled, or a read occurs from the receive fifo during a timeout period of approximately 1.28 msec (the time it takes to transfer 4 bytes over the midi communication channel). in this case, the interrupt request is de-asserted when either new data is received by the communication engine or data is read from the receive fifo. the transmit buffer empty event refers to the case in which the transmit buffer/fifo of the midi port can still accept data to transmit. an interrupt request is asserted by the midi port to indicate a transmit buffer empty event in one of the following cases: ? the midi port is in pass-thru mode and the transmit buffer is empty. in this case, the interrupt request is de-asserted once a byte is written to the transmit buffer. ? the midi port is in uart mode and the transmit fifo is empty. in this case, the interrupt request is de-asserted once the transmit fifo is filled with at least three bytes. after hardware reset, interrupts are asserted by the midi port only in response to a receive data ready event. interrupt assertion in response to transmit buffer empty events can be enabled by setting writing 1 t o bit 1 o f the mcntl register. interrupt assertion in response to receive data ready events can be disabled by writing 0 to bit 3 of the mcntl register.
10.0 musical instrument digital interface (midi) port (continued) 171 www.national.com 10.2.9 enhanced midi port features the midi port supports the following modes/operations, which are not part of the legacy definition of the midi port: l transmit in pass-thru. l loopback mode. l midi thru. l mdtx pin masking. transmit in pass-thru. when the midi port is operated in pass-thru mode, transmit is disabled by default. to enable it, write 1 to bit 4 of the mcntl register. loopback mode. the midi serial data transmit signal is routed internally to the midi serial data receive signal. this causes all the data transmitted by the midi port to also be received. loopback mode can be used as a mode for testing the midi port or its software. to enable it, write 1 to bit 7 of the mcntl register. midi thru. the midi serial data receive signal is routed internally to the midi serial data transmit signal. this causes any incoming stream of pulses received via the mdrx pin to be driven immediately on the mdtx pin. this feature allows the midi port to be connected as a link in a chain of several midi devices. in parallel to routing the midi receive signal to the midi transmit signals, the incoming serial data is also received by the midi port itself. to enable it, write 1 t o bit 6 o f the mcntl register. mdtx pin masking. mdtx pin masking forces this pin to remain at a high level. this causes all transmit processes to occur without physically driving the serial data via the mdtx pin. writing 1 t o bit 2 o f the mcntl register enables mdtx pin mask- ing. the above three features are handled by the midi signals routing control logic, which is illustrated in figure 34. figure 34. midi signals routing control logic mdtx pin mdrx pin midi transmit signal midi receive signal loopback mode enable midi thru enable mdtx pin masking enable 0 0 1 1
10.0 musical instrument digital interface (midi) port (continued) 172 www.national.com 10.3 midi port registers the following abbreviations are used to indicate the register type: l r/w = read/write. l r = read from a speci?c address returns the value of a speci?c register. w rite to the same address is to a different register. l w = w rite. l ro = read only. l r/w1c = read/write 1 t o clear. w riting 1 t o a bit clears it to 0. writing 0 has no effect. 10.3.1 midi port register map the following table lists the midi port registers. for the midi port register bitmap, see section 10.4. 10.3.2 midi data in register (mdi) this read register is used for reading data received by the midi port and status information returned by the midi port in response to a previously issued command. when the fifos of the midi port are enabled, reading from this offset returns the next byte taken out of the receive fifo. location: offset 00h type: r 10.3.3 midi data out register (mdo) this write register is used for writing data to be transmitted by the midi port. when the fifos of the midi port are enabled, writing to this offset puts the data byte into the transmit fifo. location: offset 00h type: w offset mnemonic register name type section 00h mdi midi data in r 10.3.2 00h mdo midi data out w 10.3.3 01h mstat midi status r 10.3.4 01h mcom midi command w 10.3.5 02h mcntl midi control w/r 10.3.6 bit 76543210 name data in reset xxxxxxxx bit 76543210 name data out reset xxxxxxxx
10.0 musical instrument digital interface (midi) port (continued) 173 www.national.com 10.3.4 midi status register (mstat) this read register provides status information regarding the functional blocks of the midi port. location: offset 01h type: r 10.3.5 midi command register (mcom) this write register is a port via which commands are issued by the host to the midi port. location: offset 01h type: w bit 76543210 name rx buffer empty tx buffer full rx fifo full midi port operation mode rx overrun error tx fifo not empty reserved reset 10000000 bit description 7 rx buffer empty. when set to 1, it indicates that the receive buffer in pass-thru mode, o r the fifo in uart mode, i s empty. when set to 0, it indicates that the receive buffer or fifo contain data that can be read via the mdi register. 0: not empty 1: empty (default) 6 tx buffer full. when set to 1, it indicates that the transmit buffer or fifo cannot accept any more data. when set to 0, it indicates that the transmit buffer or fifo can accept more data written to the mdo register. 0: not full (default) 1: full 5 rx fifo full. when set to 1, it indicates that the receive fifo cannot accept any more received data bytes. when set to 0, it indicates that the receive fifo can accept more received data bytes. this bit is forced to 0 when the fifos are disabled. 0: not full or disabled (default) 1: full 4 midi port operation mode. when set to 1, it indicates that the midi port is currently operating in uart mode. when set to 0, it indicates that the midi port is currently operating in pass-thru (non-uart) mode. 0: pass-thru mode (default) 1: uart mode 3 rx overrun error. this bit is cleared to 0 when the mstat register is read. an overrun error is de?ned as the state in which one or more data bytes have been received by the midi port while the receive buffer, o r fifo, was full. 0: no overrun error (default) 1: overrun error 2 tx fifo not empty. this bit is forced to 0 when the fifos are disabled. 0: empty or disabled (default) 1: not empty 1-0 reserved. bit 76543210 name command byte reset xxxxxxxx
10.0 musical instrument digital interface (midi) port (continued) 174 www.national.com 10.3.6 midi control register (mcntl) this register controls enhanced midi functions. location: offset 02h type: r/w bit 76543210 name loopback mode enable midi thru enable reserved pass-thru transmit enable rx data ready interrupt enable mdtx pin masking enable tx buffer empty interrupt enable rx fifo enable for pass-thru mode reset 00001001 required 0 bit description 7 loopback mode enable. when enabled, the midi receive signal is internally connected to the midi transmit signal. 0: disabled (default) 1: enabled 6 midi thru enable. when enabled, the mdrx pin is internally connected to the mdtx pin, which then re?ects the midi receive signal. when disabled, the mdtx pin is driven with data coming from the midi port transmit engine. 0: disabled (default) 1: enabled 5 reserved. 4 pass-thru transmit enable. when enabled, data is transmitted in pass-thru (non-uart) mode. 0: disabled (default) 1: enabled 3 rx data ready interrupt enable. when enabled, an interrupt request is asserted in response to a receive data ready event. 0: disabled 1: enabled (default) 2 mdtx pin masking enable. when enabled, the mdtx pin is constantly driven high by the midi port. when disabled, mdtx serves a s the midi port transmit line. 0: disabled (default) 1: enabled 1 tx buffer empty interrupt enable. when enabled, an interrupt request is asserted in response to a transmit buffer empty event. 0: disabled (default) 1: enabled 0 rx fifo enable for pass-thru mode . when this bit is set to 1, the receive fifo is enabled in pass-thru mode. this bit is ignored in uart mode. 0: disabled 1: enabled (default)
10.0 musical instrument digital interface (midi) port (continued) 175 www.national.com 10.4 midi port bitmap register bits offset mnemonic 76543210 00h mdi data in 00h mdo data out 01h mstat rx buffer empty tx buffer full rx buffer full midi port operation mode rx overrun error tx fifo empty reserved 01h mcom command byte 02h mcntl loopback mode enable midi thru enable reserved pass- thru transmit enable rx data ready interrupt enable mdtx pin masking enable tx buffer empty interrupt enable rx fifo enable for pass- thru mode
176 www.national.com 11.0 voltage level monitor (vlm) 11.1 overview the voltage level monitor (vlm) is an a/d converter that monitors various voltages in the system, reports their values to system monitoring software and can set an alarm when any of these voltages is outside a specified range. the vlm con- forms to ldcm and dmi requirements for system monitoring. the vlm can sense up to 14 voltage values. seven sources are external and can be applied per system requirements. four values are internal and used for v sb ,v dd ,v bat and av dd .v sb ,v dd and av dd are internally divided by 2 t o allow detection of voltage both over and under the specified range. ts1, ts2 and ts3 inputs are used for temperature measurement using a thermistor. the host can query the various voltage readout values and configure the vlm to generate an alarm signal when the volt- age is outside a specified range (below vi low or above vi high , where i i s the channel number). the alarm can generate an interrupt internally and/or output to a pin of the device. 11.2 functional description the vlm incorporates an 8-bit a/d converter and a set of control, configuration and status registers and digital circuitry that controls its operation. figure illustrates the structure of the vlm module. the vlm measures the various input voltages periodically, as defined by the conversion rate setting (see section 11.5.9). at the beginning of each period, a measurement trigger is issued, which starts a burst of conversion operations. the burst includes scanning all enabled channels starting from channel 0. to guarantee the stability of the signal at the input of the a/d converter, a delay is added between the end of each conversion and the beginning of the next. the delay between samples should be adjusted according to the resistance and capacitance of the input source. see section 11.7.1 for information on how to calculate the sampling delay; see section 11.5.9 for the associated programing model. the voltage readout is an unsigned integer between 0 and 255. section 11.2.1 describes how the readout is converted to a voltage value. the vlm is designed to preserve indication of failures by disabling the conversion whenever the slps3 input becomes ac- tive (i.e., v dd is expected to drop) and whenever an error is detected. the conversion and register updates resume only after power is restored and normal system operation resumes. to prevent loss of error condition flagging, the conversions for voltage measurement channels (0 through 10 only) that are out of range are stopped until the alarm status is cleared. whenever slps3 is not available in the system, the slps3 input should be tied to 1 and the software should disable the measurements before the power fails or ignore and clear any pending error flags after power is restored.
11.0 voltage level monitor (vlm) (continued) 177 www.national.com figure 35. vlm functional diagram 11.2.1 voltage measurement, channels 0 through 10 voltage is measured relative to (2.45 0.05) * v ref (where v ref is the voltage of the v ref input or the internal reference volt- age). the results are output to the read channel voltage (rdchv) register associated with the channel. the voltage mea- sured is: v i = (2.45 0.05) * v ref * rdchv i / 256 v sb ,v dd and av dd are internally divided by two. therefore, the readouts are half their actual values. when external dividers are used to scale input voltage to within the dynamic range of the a/d converter, appropriate scale factors should be taken into account. v high and v low limits, alarm output, irq and smi the voltage reading is compared to two limits: v high and v low . i f the voltage reading is outside any of these limits, the respective status bit (channel high limit exceeded or channel low limit exceeded) in the vchcfst register is set. the status bit stays active until it is cleared by the software. an alarm status bit in the vevsts0 or vevsts1 register is set when the channel high limit exceeded or the channel low limit exceeded bit for the respective channel is set. sib a/d converter 14:1 analog ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 mux vlm clock divider clock v in0 avi0 control logic status, data & con?g registers a/d avi6 v in0 v in6 ad8 ad12 ad11 ad13 v sb v dd ad9 v bat ts1 ts2 ts3 low + high + delay start avss irq alarm smi irq aler t smi converter analog power 3.3v v ref internal v ref av dd ad10 av dd v sb power overtemp + o ts } } to vlm config to tms config ref *(2.45 0.05)
11.0 voltage level monitor (vlm) (continued) 178 www.national.com the alarm output is used to indicate to the system that a voltage outside the high/low limits was detected. the alarm output enable bit in the vchcfst register enables the alarm output to be active when the channel high limit exceeded or the channel low limit exceeded status bit in the vchcfst register is set. the smi output generates an interrupt if any enabled smi event occurs. each bit in the vevsts0/1 register has a corre- sponding smi enable bit in the vevsmi0/1 register. when any status bit and its corresponding smi enable bit are set, the smi output is active. the irq output generates an interrupt if any enabled irq event occurs. each bit in the vevsts0/1 register has a corre- sponding irq enable bit in the vevirq0/1 register. when any status bit and its corresponding irq enable bit are set, the irq output is active. alarm response read sequence when the vlm activates the alarm output, the host should respond by reading the vevsts0 and vevsts1 registers. it should then access the register of each of the channels whose bit is set in the vevsts0 and vevsts1 registers and clear these bits by writing 1 to each of them. 11.2.2 thermistor-based temperature measurement, channels 11 to 13 the vlm module can measure environmental temperature by using thermistors. this feature is supported over channels 11 to 13. the temperature measurement under this scheme is based on a voltage divider between av dd and av ss where one of the two resistors is a thermistor. see figure 36. the translation of voltage to temperature is determined by the parameters of the thermistor in use. the values in the registers with the results and limits are defined by the result of the voltage measurement. for the channels that support temperature measurement, standard temperature monitoring functions are provided: low- and high-temperature alert and overtemper- ature shutdown. 11.2.3 v os , v high and v low limits, ots and alert output, irq and smi the voltage reading is compared to three limits: v os ,v high and v low . i f the voltage reading is outside any of these limits, the respective status bit (channel overtemperature limit exceeded, channel high limit exceeded or the channel low limit exceeded) in the vchcfst register is set. the status bit will stay active until it is cleared by the software. an alert status bit in the vevsts0/1 register is set when the channel high limit exceeded, the channel low limit exceeded or the over- temperature event bit for the respective channel is set. the ots output is used to indicate to the system that the overtemperature limit has been exceeded. the ots output enable bit in the vchcfst register enables the ots output to be active when the ots status of the channel is active. the alert output is used to indicate to the system that the current temperature is outside the high/low limits. the alert output enable bit in the vtchcfst register enables the alert output to be active when the channel high limit exceeded or the channel low limit exceeded status bit in the vchcfst register is set. [the alert signal is not connected in the 365 and 366.] the smi output generates an interrupt if any enabled smi event occurs. each bit in the vevsts1 register has a correspond- ing smi enable bit in the vevsmi1 register. when any status bit and its corresponding smi enable bit are set, the smi output is active. the irq output generates an interrupt if any enabled irq event occurs. each bit in the vevsts1 register has a correspond- ing irq enable bit in the vevirq1 register. when any status bit and its corresponding irq enable bit are set, the irq output is active. figure 36. measuring temperature using thermistors r av dd nts tsi pts r tsi av dd av ss av ss
11.0 voltage level monitor (vlm) (continued) 179 www.national.com aler t response read sequence when the vlm activates its alert output, the host should respond by reading the vevsts0 and vevsts1 registers. it should then access the register of each of the channels that has its respective bit set and clear the highv and lowv status bits by writing 1 to each of them. 11.2.4 power-on reset default states vlm power-on default conditions are: ? all registers are loaded with their default values. ? the alarm output, irq and smi are disabled. 11.2.5 standby mode standby mode is enabled by setting the standby mode enable bit in the vlmcfg register. standby mode reduces power supply current by disabling new measurements, but register values are retained and the registers can be accessed by soft- ware (as usual). 11.3 analog supply connection 11.3.1 recommendations power is supplied to the analog parts of the a/d converter through two dedicated analog power pins: av dd and av ss . this ensures effective isolation of the analog parts from noise caused by the digital parts. the digital parts of the vlm are supplied via v sb . to obtain the best performance, bear in mind the following recommendations (see also details in figure 37). ground connection. the analog ground pin, av ss , should be connected at only one point to the digital ground pins. at this point, the following ground connections should also be made: ? the decoupling capacitors of the analog supply av dd pin. ? the reference voltage v ref pin. ? the four digital supply v sb pins. ? the ground reference of the input signals to the a/d converter. low-impedance ground layers also improve noise isolation. power connection. the analog supply pin, av dd , should be connected to a low-noise power supply, 3.3v. it is recom- mended to supply the av dd pin through an external lc or rc filter. an example of an rc filter [r 1 and (c 2 +c 3 )] is shown in figure 37. decoupling capacitors. the following decoupling capacitors should be used: ? digital v sb : place one capacitor of 0.1 m f o n each v sb pin as close as possible to the pin (4 x c 4 ). also, place one 10- 47 m f tantalum capacitor (c 5 ) on the common net as close as possible to the chip. ? analog av dd : place a 0.1 m f capacitor and a 10-47 m f tantalum capacitor on the av dd pins (c 3 and c 2 ) a s close as possible to the pin. ? v ref : place a low-leakage, non-polarized, 0.47 m f capacitor (c 1 ) as close as possible to the v ref pin.
11.0 voltage level monitor (vlm) (continued) 180 www.national.com figure 37. analog power supply 11.3.2 reference voltage analog input voltage is measured relative to (2.45 0.05)*v ref .v ref may be either internal or external. when an internal v ref is used, a capacitor should be connected between the v ref pin and av ss . the v ref default setting is for external. this default prevents contention between the internal and external v ref . note that the v ref setting is common to both the vlm and the tms modules. if either of these modules is configured to use internal reference voltage, the internal reference voltage is used by both modules. 11.4 register bank overview the vlm uses register banks to enable host access to its registers. the vlm has 10 common registers in addition to five registers that are located in each of the 13 banks. the common registers include configuration and status information com- mon to all the channels. each of the banks is associated with one channel and holds its readout, configuration and status information. all registers use the same 16-byte address space to indicate offsets 00h through 0fh. the active bank must be selected by the software. the vlm bank selection (vlmbs) register, which is common to all banks, selects the active banks (see figure 38). the default bank selection after system reset is 0. figure 38. register bank architecture gnd digital ground layer power analog av dd c 4 0.1 c 3 0.1 av ss analog ground layer power supply r 1 + 10 w c 2 ad0 ad6 ad0 ad6 c 5 22 + 22 v in m f m f m f m f 3.3 v v ref v ref c 1 0.47 m f v ref v sb offset 0bh offset 0eh offset 0fh vlmbs (09h) common registers all banks offset 0ah bank 1 bank 0 offset 08h . offset 00h . . for } bank 13
11.0 voltage level monitor (vlm) (continued) 181 www.national.com 11.5 vlm registers the register maps in this chapter use the following abbreviations for type: ? r/w = read/write. ? r = read from a speci?c address returns the value of a speci?c register. w rite to the same address is to a different register. ? w = w rite. ? ro = read only. ? r/w1c = read/write 1 t o clear. w riting 1 t o a bit clears it to 0. writing 0 has no effect. 11.5.1 vlm register map table 51. vlm control and status register map table 52. vlm channel register map (one per channel) offset mnemonic register name type section 00h vevsts0 voltage event status 0 ro 11.5.2 01h vevsts1 voltage event status 1 ro 11.5.3 02h vevsmi0 voltage event to smi 0 r/w 11.5.4 03h vevsmi1 voltage event to smi 1 r/w 11.5.5 04h vevirq0 voltage event to irq 0 r/w 11.5.6 05h vevirq1 voltage event to irq 1 r/w 11.5.7 06h vid voltage id varies per bit 11.5.8 07h vcnvr voltage conversion rate r/w 11.5.9 08h vlmcfg vlm con?guration r/w 11.5.10 09h vlmbs vlm bank select r/w 11.5.11 offset mnemonic register name type section 0ah vchcfst voltage channel configuration and status varies per bit 11.5.12 0bh rdchv read channel voltage ro 11.5.13 0ch chvh channel voltage high limit r/w 11.5.14 0dh chvl channel voltage low limit r/w 11.5.15 0eh otsl overtemperature shutdown limit r/w 11.5.16 0fh reserved
11.0 voltage level monitor (vlm) (continued) 182 www.national.com 11.5.2 voltage event status register 0 (vevsts0) this register indicates which of the corresponding eight vlm events has occurred. location: offset 00h type: ro 11.5.3 voltage event status register 1 (vevsts1) this register indicates which of the corresponding vlm events has occurred. location: offset 01h type: ro bit 76543210 name vsb alarm event status avi6 alarm event status avi5 alarm event status avi4 alarm event status avi3 alarm event status avi2 alarm event status avi1 alarm event status avi0 alarm event status reset 00000000 bit description 7 vsb alarm event status. this channel measures the internal v sb power, using v sb /2. 0: voltage level within limits (default) 1: high or low limit exceeded 6-0 analog voltage inputs 6-0 alarm event status. 0: voltage level within limits (default) 1: high or low limit exceeded bit 76543210 name reserved tms3 alert or o ts event status tms2 alert or o ts event status tms1 alert or o ts event status av dd alarm event status vbat alarm event status vdd alarm event status reset 0 0000000 bit description 7-6 reserved. 5 tms3 alert or o ts event status. 0: voltage level within limits (default) 1: o ts, high or low limit exceeded 4 tms2 alert or o ts event status. 0: voltage level within limits (default) 1: o ts, high or low limit exceeded 3 tms1 alert or o ts event status. 0: voltage level within limits (default) 1: o ts, high or low limit exceeded
11.0 voltage level monitor (vlm) (continued) 183 www.national.com 11.5.4 voltage event to smi register 0 (vevsmi0) this register is one of two registers that controls event routing to smi. location: offset 02h type: r/w 2 av dd alarm event status. this channel measures the internal av dd power, using av dd /2. 0: voltage level within limits (default) 1: high or low limit exceeded 1 vbat alarm event status. this channel measures the v bat power input. 0: voltage level within limits (default) 1: high or low limit exceeded 0 vdd alarm event status. this channel measures the internal v dd power, using v dd /2. 0: voltage level within limits (default) 1: high or low limit exceeded bit 76543210 name vsb event to smi enable avi6 event to smi enable avi5 event to smi enable avi4 event to smi enable avi3 event to smi enable avi2 event to smi enable avi1 event to smi enable avi0 event to smi enable reset 00000000 bit description 7 vsb event to smi enable. 0: disabled (default) 1: enabled 6-0 avi6-0 event to smi enable . 0: disabled (default) 1: enabled bit description
11.0 voltage level monitor (vlm) (continued) 184 www.national.com 11.5.5 voltage event to smi register 1 (vevsmi1) this register is one of two registers that controls event routing to smi. location: offset 03h type: r/w bit 76543210 name reserved tms3 event to smi enable tms2 event to smi enable tms1 event to smi enable av dd event to smi enable vbat event to smi enable vdd event to smi enable reset 0 0000000 bit description 7-6 reserved. 5 tms3 event to smi enable. 0: disabled (default) 1: enabled 4 tms2 event to smi enable. 0: disabled (default) 1: enabled 3 tms1 event to smi enable. 0: disabled (default) 1: enabled 2 av dd event to smi enable. 0: disabled (default) 1: enabled 1 vbat event to smi enable. 0: disabled (default) 1: enabled 0 vdd event to smi enable. 0: disabled (default) 1: enabled
11.0 voltage level monitor (vlm) (continued) 185 www.national.com 11.5.6 voltage event to irq register 0 (vevirq0) this register is one of two registers that controls event routing to irq. location: offset 04h type: r/w 11.5.7 voltage event to irq register 1 (vevirq1) this register is one of two registers that controls routing to irq. location: offset 05h type: r/w bit 76543210 name vsb event to irq enable avi6 event to irq enable avi5 event to irq enable avi4 event to irq enable avi3 event to irq enable avi2 event to irq enable avi1 event to irq enable avi0 event to irq enable reset 00000000 bit description 7 vsb event to irq enable. 0: disabled (default) 1: enabled 6-0 avi6-0 event to irq enable. 0: disabled (default) 1: enabled bit 76543210 name reserved tms3 event to irq enable tms2 event to irq enable tms1 event to irq enable av dd event to irq enable vbat event to irq enable vdd event to irq enable reset 0 0000000 bit description 7-6 reserved. 5 tms3 event to irq enable. 0: disabled (default) 1: enabled 4 tms2 event to irq enable. 0: disabled (default) 1: enabled 3 tms1 event to irq enable. 0: disabled (default) 1: enabled
11.0 voltage level monitor (vlm) (continued) 186 www.national.com 11.5.8 voltage id register (vid) this register indicates the configuration of the power supply regulator for the cpu(s). location: offset 06h type: varies per bit 2 av dd event to irq enable. 0: disabled (default) 1: enabled 1 vbat event to irq enable. 0: disabled (default) 1: enabled 0 vdd event to irq enable. 0: disabled (default) 1: enabled bit 76543210 name cpu vid select reserved vid value reset 0 0 0 xxxxx bit type description 7-6 r/w cpu voltage id select. this ?eld selects which of the cpus vid pins is read in the voltage id value ?eld. bits 7 6 voltage id 0 0 cpu0 (default) 0 1 cpu1 other reserved 5 reserved. 4-0 ro voltage id value. returns the current value of the vid inputs selected by the cpu vid select ?eld. the pins used for the vid ?eld are de?ned by vid0 and vid1 route select bits of the superi/o con?guration 5 register (see section 2.8.6). bit description
11.0 voltage level monitor (vlm) (continued) 187 www.national.com 11.5.9 voltage conversion rate register (vcnvr) this register indicates time related specification for the vlm. location: offset 07h type: r/w bit 76543210 name reserved channel delay conversion period reset 00000000 bit description 7-6 reserved. 5-3 channel delay. these bits de?ne the sampling delay. the sampling delay helps guarantee the accuracy of the sampled value when switching from one channel to another. bits 5 4 3 delay ( m sec) 0 0 0 4 0 (default) 001 80 0 1 0 160 others reserved 2-0 conversion period. these bits de?ne the period of time between reconversions of all enabled channels. v bat (channel 9) is converted at the ?rst of every 1024 conversion periods. bits 2 1 0 conversion period 0 0 0 2 seconds (default) 0 0 1 1 second 0 1 0 0.5 seconds 0 1 1 0.1 seconds 1 0 0 0.05 seconds 1 0 1 0.02 seconds others reserved
11.0 voltage level monitor (vlm) (continued) 188 www.national.com 11.5.10 vlm configuration register (vlmcfg) this register selects the channels and sets global configuration (not channel specific) values. location: offset 08h type: r/w 11.5.11 vlm bank select register (vlmbs) this register selects a bank and its associated channels. location: offset 09h type: r/w bit 76543210 name reserved external vref standby mode enable reset 00000011 bit description 7-2 reserved. 1 external vref. this bit selects either the internal or external reference voltage as a reference for the a/d converter. note that if either the vlm or tms specify the use of an internal v ref , the internal v ref will be used by both these modules. 0: internal v ref in use 1: external v ref in use (default) 0 standby mode enable. 0: monitoring operation enabled 1 standby mode enabled (default) bit 76543210 name reserved bank select value reset 00000000 bit description 7-5 reserved. 4-0 bank select value. these bits contain the binary value that selects a bank and its associated channels for con?guration and viewing. 4 3 2 1 0 bank function 0 0 0 0 0 0 channel 0 (default) 0 0 0 0 1 1 channel 1 ...... 0 1 0 1 0 1 0 channel 10 0 1 0 1 1 1 1 channel 11 - temperature ...... 0 1 1 0 1 1 3 channel 13 - temperature other reserved
11.0 voltage level monitor (vlm) (continued) 189 www.national.com 11.5.12 voltage channel configuration and status register (vchcfst) this register indicates the current channel status. location: offset 0ah - banks 0 through 10 type: varies per bit location: offset 0ah - bank 11 through 13 type: varies per bit bit 76543210 name end of conversion reserved alarm output enable reserved channel high limit exceeded channel low limit exceeded channel enable reset 00000000 bit 76543210 name end of conversion reserved alarm output enable channel overtemp limit exceeded channel high limit exceeded channel low limit exceeded channel enable reset 00000000 bit type description 7 rw1c end of conversion. this bit indicates that the rdchv register (see next page) holds new data. it is set when new data is written into rdchv as a result of completing a conversion for this channel. it is cleared by writing 1 t o this bit. 0: no new data (default) 1: new data not yet read 6-5 reserved. 4 r/w alarm output enable. 0: disabled (default) 1: enabled 3 rw1c channel overtemperature limit exceeded . banks 11 through 13. 0: voltage read, indicating overtemperature limit exceeded (default) 1: o ts signal set, indicating overtemperature limit exceeded 2 rw1c channel high limit exceeded. 0: voltage lower than limit (default) 1: voltage higher than limit 1 rw1c channel low limit exceeded. 0: voltage higher than limit (default) 1: voltage lower than limit 0 r/w channel enable. 0: disabled (default) 1: enabled
11.0 voltage level monitor (vlm) (continued) 190 www.national.com 11.5.13 read channel voltage register (rdchv) this register holds the last voltage readout for each channel. the value is an 8-bit unsigned integer of the voltage measured by the channel. location: offset 0bh - banks 0 to 13 type: ro 11.5.14 channel voltage high limit register (chvh) this register holds the voltage high limit value that is compared with the voltage reading. location: offset 0ch - banks 0 through 13 type: r/w 11.5.15 channel voltage low limit register (chvl) this register holds the voltage low limit value that is compared with the voltage reading. location: offset 0dh - banks 0 through 13 type: r/w 11.5.16 overtemperature shutdown limit register (otsl) this register defines the overtemperature shutdown limit for banks 11 to 13. its power-up default is the maximum voltage readout. location: offset 0eh banks 11 to 13 type: r/w bit 76543210 name channel voltage value reset 00000000 bit 76543210 name channel voltage high limit value reset 11111111 bit 76543210 name channel voltage low limit value reset 00000000 bit 76543210 name overtemperature shutdown limit value reset 11111111
11.0 voltage level monitor (vlm) (continued) 191 www.national.com 11.6 vlm register bitmap 11.6.1 vlm control and status registers 11.6.2 vlm channel registers register bits offset mnemonic 7 6 5 4 3 2 1 0 00h vevsts0 vsb alarm event status avi6 alarm event status avi5 alarm event status avi4 alarm event status avi3 alarm event status avi2 alarm event status avi1 alarm event status avi0 alarm event status 01h vevsts1 reserved tms3 alert or o ts event status tms2 alert or o ts event status tms1 alert or o ts event status av dd alarm event status vbat alarm event status vdd alarm event status 02h vevsmi0 vsb event to smi enable avi6 event to smi enable avi5 event to smi enable avi4 event to smi enable avi3 event to smi enable avi2 event to smi enable avi1 event to smi enable avi0 event to smi enable 03h vevsmi1 reserved tms3 event to smi enable tms2 event to smi enable tms1 event to smi enable av dd event to smi enable vbat event to smi enable vdd event to smi enable 04h vevirq0 vsb event to irq enable avi6 event to irq enable avi5 event to irq enable avi4 event to irq enable avi3 event to irq enable avi2 event to irq enable avi1 event to irq enable avi0 event to irq enable 05h vevirq1 reserved tms3 event to irq enable tms2 event to irq enable tms1 event to irq enable av dd event to irq enable vbat event to irq enable vdd event to irq enable 06h vid cpu vid select reserved vid value 07h vcnvr reserved channel delay conversion period 08h vlmcfg reserved external vref standby mode en- able 09h vlmbs reserved bank select value register bits offset mnemonic 76543210 0ah (bank 0-10) vchcfst end of conversion reserved alarm output enable reserved channel high limit exceeded channel low limit exceeded channel enable 0ah (bank 11-13) vchcfst end of conversion reserved alarm output enable channel overtemp limit exceeded channel high limit exceeded channel low limit exceeded channel enable 0bh (bank 0-13) rdchv channel voltage value
11.0 voltage level monitor (vlm) (continued) 192 www.national.com 11.7 usage hints 11.7.1 calculating the channel delay the channel delay is the interval between the time a new channel is selected and the time the channel voltage can be mea- sured. the reason for this delay is to allow the voltage to charge all internal capacitors to guarantee accuracy of the mea- surement. this delay period depends on characteristics of the input (resistance and capacitance) and of the external circuit. figure 39 shows the schematic of the input and its equivalent r-c circuit. the sampling time should be long enough to guar- antee that the voltage settles on the capacitor c s . the voltage on c s should be stable before the measurement starts. the r ain and c ain values represent the input path serial resistance and parallel capacitance. r ain is the serial resistance of the multiplexer, sample & hold switch and other parasitic resistors. c ain is the parallel capacitance of the input pin, pad, lead- frame, c s , etc. the required sampling time is determined by r ain and c ain together with the input source resistance r source and parasitic capacitance c p . table 53 can be used as a reference for calculating the sample time. channel delay of the vcnvr register should be programmed accordingly. 0ch (bank 0-13) chvh channel voltage high limit value 0dh (bank 0-13) chvl channel voltage low limit value 0eh (bank 11-13) otsl overtemperature shutdown limit value 0fh reserved register bits r ain c ain input signal r source figure 39. analog input schematic diagram and equivalent r-c circuit c s analog ad0 ad1 ad2 ad3 ad4 ad5 ad6 mux v in r source v in c p c p is the parasitic capacitor including the external r ain is the equivalent serial resistance of all serial elements inside the chip (pin, bonding, mux, sample & elements (pcb capacitance etc.). hold switch, layout). c s is the sampling capacitor. c ain is the equivalent parallel capacitance of the chip parasitic capacitances and the c s capacitor.
11.0 voltage level monitor (vlm) (continued) 193 www.national.com 11.7.2 measuring out of range positive and negative voltages only voltages within the range of 0v to (2.45 0.05)*v ref can be measured by the module. to measure voltages out of this range, any of the external measurement pins can be used with the addition of external resistors that should be used as volt- age dividers. (see figure 40.) 11.7.3 obtaining the specified vlm/tms accuracy to obtain the specified vlm/tms accuracy, see section 12.5.5 on page 208: table 53. delay setting example external elements delay time (ns) r source [k w ] c p [pf] 5 0.1 15 1 110 10 900 30 3200 27.5 0.1 25 1 210 10 2220 30 7900 50 0.1 45 1 430 10 3350 30 11400 figure 40. measurement out of positive and negative voltages r 1 v in (12v) r 2 av i r 1 r 2 av i v in (-12v) av dd av ss av ss
194 www.national.com 12.0 temperature sensor (tms) 12.1 overview the temperature sensor (tms) is a diode input temperature sensor that consists of a delta-sigma analog to digital (a/d) converter and a digital overtemperature detector. both of these elements conform to advance configuration and power in- terface (acpi) requirements for thermal management. the tms senses its own temperature and the temperature of two target ics by measuring the voltage drop of diode(s) placed on the target ics die. a host can query the tms at any time to read the temperature of the remote diode(s) in addition to the local temperature. an alert interrupt output becomes active when the temperature goes above t high or below t low . the host may program the two thresholds for each sensing channel to define an operation window. overtemperature shutdown ( ots) output becomes active when the temperature exceeds the programmable limit t os . 12.2 functional description the tms incorporates a band-gap temperature sensor using a local and remote diode(s) and an 8-bit delta-sigma analog- to-digital converter (a/d converter). once enabled and put in active (non-standby mode), the tms continuously measures temperature of up to one internal diode and two remote diodes. tms readings are available at all times via the host interface. when slps3 input becomes inactive, the conversion is stopped and no new results are generated until both slps3 be- comes active and the internal wake up sequence is completed. tms registers are maintained by v sb during this period. a digital comparator is also incorporated to compare temperature readings to user-programmable limits. ots output indi- cates that the result of the comparison exceeds the limit preset in the channel overtemperature limit register. alert output indicates that the result of the comparison is not within limits preset in the channel temperature high or low limit (chth and chtl) registers. figure 41 shows a simplified block diagram of the tms. it represents only the local diode and one remote diode (even though there are actually two remote diodes in addition to the local diode and one or three o ts signals, one for each diode sensor or combined). figure 41. tms simpli?ed block diagram temperature sensor circuitry dpi dni d-s 8-bit a/d converter diode selector control logic temperature readout overtemp. shutdown setpoint high and low limit setpoints conversion rate o ts irq smi tms module aler t overtemp high low enable and config logic enable bits v dd v ss v sb } to tms config
12.0 temperature sensor (tms) (continued) 195 www.national.com 12.2.1 register bank overview three register banks control tms operation. the first part of each bank is a set of registers common to all banks. the second part of each bank contains registers which are specific to that bank. all registers use the same 16-byte address space to indicate offsets 00h through 0fh. the software selects the currently active bank using the bank select register (tmsbs) see figure 42. bank 0 is selected after reset. figure 42. register bank architecture 12.2.2 t os , t high and t low limits, ots and alert output, irq and smi the temperature reading is compared to three limits: t os ,t high and t low . i f the temperature reading is outside any of these limits, the respective status bit (channel overtemperature limit exceeded, channel temp high limit exceeded or channel temp low limit exceeded) in the tchcfst register is set. the status bit stays active until it is cleared by the soft- ware. an alert status bit in the tevsts register is set when the channel temp high limit exceeded or channel temp low limit exceeded bit for the respective channel is set. the channels overtemperature event status in the tevsts reg- ister is set when the channel overtemperature limit exceeded bit is set. the ots output is used to indicate to the system that the overtemperature limit has been exceeded. the ots output enable bit in the tchcfst register enables the ots output to be active when the ots status of the channel is active. the alert output is used to indicate to the system that the current temperature is outside the high/low limits. the alert output enable bit in the tchcfst register enables the alert output to be active when the channel temp high limit ex- ceeded or the channel temp low limit exceeded status bit in tchcfst register is set. the smi output generates an interrupt if any enabled smi event occurs. each bit in the tevsts register has a correspond- ing smi enable bit in the tevsmi register. when any status bit and its corresponding smi enable bit are set, the smi output is active. the irq output generates an interrupt if any enabled irq event occurs. each bit in the tevsts register has a correspond- ing irq enable bit in the tevirq register. when any status bit and its corresponding irq enable bit are set, the irq output is active. . offset 0eh tmsbs (09h) common registers all banks offset 0ah bank 1 bank 0 offset 08h . offset 00h . . for bank 2 } . .
12.0 temperature sensor (tms) (continued) 196 www.national.com figure 43. o ts and aler t temperature response diagrams 12.2.3 alert response read sequence the read channel temperature register (rdcht) holds the temperature value most recently read from the channel. the temperature event status register (tevsts) indicates any alert detected as long as v sb is maintained. alerts are cleared by software. when an irq or smi is received, check the tevsts register to see which of the sensors detected an out-of-limit readout, access the channel readouts, read the current value and status information and clear any pending status bits. 12.2.4 power-on reset default states tms always powers up in a known state. tms power-up default conditions are: 1. local temperature set to 0 c. 2. remote temperature set to 0 c until the tms senses a diode present on d+ and d- input pins. 3. status register set to 00h. 4. command register set to 00h; alert and ots enabled and standby mode deactivated. 5. local and remote t os set to 127 c. 6. local and remote t high set to 127 c. 7. local and remote t low set to -55 c. ots indicates when temperature is sampled by the a/d converter. t os1 t os2 t high t low alert indicates when temperature is sampled by the a/d converter. a: alert signal b: ots signal t os2 t low2 ots indicates when temperature is sampled by the a/d converter. t high2 t low1 t high1 t os1 alert c: combined alert and ots signals
12.0 temperature sensor (tms) (continued) 197 www.national.com 12.2.5 temperature data format temperature data is stored in the rdcht, chth, chtl and chotl registers as an 8-bit, 2s complement word with a least significant bit (lsb) equal to 1 c. table 54. temperature formats figure 44. temperature-to-digital transfer function (non-linear scale for clarity) 12.2.6 standby mode standby mode is enabled by setting the standby mode bit in the tmscfg register to 1 (default). standby mode disables the conversion process to reduce power supply current. during standby mode, all registers retain their values and can be accessed by software (as usual). 12.2.7 diode fault detection at the beginning of each conversion, the tms goes through a diode fault detection sequence. if the dxp input is shorted to v dd or floating, the temperature reading will be +127 c and the open bit of the tchcfst register is set, which activates the alert and ots outputs on completion of a conversion. if dxp is shorted to gnd or dxn, the temperature reading is o c and the temperature low limit bit of the tchcfst register is not set. temperature ( c) digital output binary h ex +125 0111 1101 7dh +25 0001 1001 19h +1 0000 0001 01h 0 0000 0000 00h -1 1111 1111 ffh -25 1110 0111 e7h 0001,1001 0000,0001 0111,1101 1111,1111 1110,0111 1100,1001 +125 c temperature +25 c output code 0000,0000 +1 c -25 c -55 c -1 c 0 c
12.0 temperature sensor (tms) (continued) 198 www.national.com 12.3 tms registers the tms registers are divided into two groups: tms control and status registers and tms channel registers. the tms channel registers are duplicated for each channel. the register maps in this chapter use the following abbreviations for type: ? r/w = read/write. ? r = read from a speci?c address returns the value of a speci?c register. w rite to the same address is to a different register. ? w = w rite. ? ro = read only. ? r/w1c = read/write 1 t o clear. w riting 1 t o a bit clears it to 0. writing 0 has no effect. 12.3.1 tms register map table 55. tms control and status register map table 56. tms channel register map (one per channel) offset mnemonic register name type section 00h tevsts temperature event status ro 12.3.2 01h reserved 02h tevsmi temperature event to smi r/w 12.3.3 03h reserved 04h tevirq temperature event to irq r/w 12.3.4 05h- 07h reserved 08h tmscfg tms con?guration r/w 12.3.5 09h tmsbs tms bank select r/w 12.3.6 offset mnemonic register name type section 0ah tchcfst temperature channel configuration and status varies per bit 12.3.7 0bh rdcht read channel temperature ro 12.3.8 0ch chth channel temperature high limit r/w 12.3.9 0dh chtl channel temperature low limit r/w 12.3.10 0eh chotl channel overtemperature limit r/w 12.3.11 0fh reserved
12.0 temperature sensor (tms) (continued) 199 www.national.com 12.3.2 temperature event status register (tevsts) this register is set to 00h on power-up of av dd . it indicates which of the corresponding three tms events has occurred. location: offset 00h type: ro bit 76543210 name reserved local overtemp event status local alert event status remote 2 overtemp event status remote 2 alert event status remote 1 overtemp event status remote 1 alert event status reset 00000000 bit description 7-6 reserved. 5 local overtemperature event status. 0: event not detected (default) 1: event detected 4 local alert event status. 0: event not detected (default) 1: event detected 3 remote 2 overtemperature event status. 0: event not detected (default) 1: event detected 2 remote 2 aler t event status. 0: event not detected (default) 1: event detected 1 remote 1 overtemperature event status. 0: event not detected (default) 1: event detected 0 remote 1 aler t event status. 0: event not detected (default) 1: event detected
12.0 temperature sensor (tms) (continued) 200 www.national.com 12.3.3 temperature event to smi register (tevsmi) this register controls temperature event routing to the smi. location: offset 02h type: r/w bit 76543210 name reserved local overtemp event to smi enable local alert event to smi enable remote 2 overtemp event to smi enable remote 2 alert event to smi enable remote 1 overtemp event to smi enable remote 1 alert event to smi enable reset 00000000 bit description 7-6 reserved. 5 local overtemperature event to smi enable. 0: disabled (default) 1: enabled 4 local alert event to smi enable. 0: disabled (default) 1: enabled 3 remote 2 overtemperature event to smi enable. 0: disabled (default) 1: enabled 2 remote 2 aler t event to smi enable. 0: disabled (default) 1: enabled 1 remote 1 overtemperature event to smi enable. 0: disabled (default) 1: enabled 0 remote 1 aler t event to smi enable. 0: disabled (default) 1: enabled
12.0 temperature sensor (tms) (continued) 201 www.national.com 12.3.4 temperature event to irq register (tevirq) this register controls temperature event routing to the irq. location: offset 04h type: r/w bit 76543210 name reserved local overtemp event to irq enable local alert event to irq enable remote 2 overtemp event to irq enable remote 2 alert event to irq enable remote 1 overtemp event to irq enable remote 1 alert event to irq enable reset 00000000 bit description 7-6 reserved. 5 local overtemperature event to irq enable. 0: disabled (default) 1: enabled 4 local alert event to irq enable. 0: disabled (default) 1: enabled 3 remote 2 overtemperature event to irq enable. 0: disabled (default) 1: enabled 2 remote 2 aler t event to irq enable. 0: disabled (default) 1: enabled 1 remote 1 overtemperature event to irq enable. 0: disabled (default) 1: enabled 0 remote 1 aler t event to irq enable. 0: disabled (default) 1: enabled
12.0 temperature sensor (tms) (continued) 202 www.national.com 12.3.5 tms configuration register (tmscfg) this register selects channels and sets global configuration (not channel-specific) values. location: offset 08h type: r/w 12.3.6 tms bank select register (tmsbs) this register selects banks and sets global configuration (not bank specific) values. location: offset 09h type: r/w bit 76543210 name reserved external vref standby mode reset 00000011 bit description 7-2 reserved. 1 external vref. this bit selects either internal or external reference voltage for conversion. note that if either the vlm or tms are configured to use the internal v ref , the internal v ref will be used by both. 0: internal vref in use 1: external vref in use (default) 0 standby mode. 0: monitoring operation enabled 1: standby mode (default) bit 76543210 name reserved bank select reset 00000000 bit description 7-4 reserved. 3-0 bank select. these bits select the bank for con?guration and viewing. bits 3 2 1 0 bank function 0 0 0 0 0 remote diode 1 0 0 0 1 1 remote diode 2 0 0 1 0 2 local diode other reserved
12.0 temperature sensor (tms) (continued) 203 www.national.com 12.3.7 temperature channel configuration and status register (tchcfst) this register is set to 00h on power-up of av dd . bits 3-1 indicate which of three temperature limits has been exceeded. write 1 to clear any of these bits. writing 0 has no effect. location: offset 0ah type: varies per bit bit 76543210 name end of conversion open o ts output enable aler t output enable channel overtemp limit exceeded channel temp high limit exceeded channel temp low limit exceeded channel enable reset 00000000 bit type description 7 r/w1c end of conversion. this bit re?ects the data in the rdcht register (see next page). it is cleared by writing 1 t o this bit. it is set when new data is written to the rdcht register. 0: no new data (default) 1: new data not yet read 6 r/w1c open. 0: no fault (default) 1: remote diode continuity (open circuit) fault 5 r/w o ts output enable. 0: disabled (default) 1: enabled 4 r/w aler t output enable. 0: disabled (default) 1: enabled 3 r/w1c channel overtemperature limit exceeded. 0: overtemperature lower than limit (default) 1: overtemperature higher than limit 2 r/w1c channel temperature high limit exceeded. 0: temperature lower than limit (default) 1: temperature higher than limit 1 r/w1c channel temperature low limit exceeded. this bit is set whenever a value lower than the value speci?ed in chtl is written into rdcht. i t i s cleared by writing 1 t o it. 0: temperature higher than limit (default) 1: temperature lower than limit 0 r/w channel enable. 0: disabled (default) 1: enabled
12.0 temperature sensor (tms) (continued) 204 www.national.com 12.3.8 read channel temperature register (rdcht) this register holds the last temperature readout for each channel. the value is an 8-bit, 2s complement word with a least significant bit (lsb) equal to 1 c of the temperature measured by the channel. location: offset 0bh type: ro 12.3.9 channel temperature high limit register (chth) this register holds the temperature high limit value that is compared with the temperature reading. location: offset 0ch type: r/w 12.3.10 channel temperature low limit register (chtl) this register holds the temperature low limit value that is compared with the temperature reading. location: offset 0dh type: r/w 12.3.11 channel overtemperature limit register (chotl) this register holds the overtemperature limit value that is compared with the temperature reading. location: offset 0eh type: r/w bit 76543210 name channel temperature value reset 00000000 bit 76543210 name channel temperature high limit value reset 01111111 bit 76543210 name channel temperature low limit value reset 11001001 bit 76543210 name channel overtemperature limit value reset 01111111
12.0 temperature sensor (tms) (continued) 205 www.national.com 12.4 tms register bitmap 12.4.1 tms control and status registers 12.4.2 tms channel registers register bits offset mnemonic 7 6 5 4 3 2 1 0 00h tevsts reserved local overtemp event status local aler t event status remote 2 overtemp event status remote 2 aler t event status remote 1 overtemp event status remote 1 aler t event status 01h reserved 02h tevsmi reserved local overtemp event to smi enable local aler t event to smi enable remote 2 overtemp event to smi enable remote 2 aler t event to smi enable remote 1 overtemp event to smi enable remote 1 aler t event to smi enable 03h reserved 04h tevirq reserved local overtemp event to irq enable local aler t event to irq enable remote 2 overtemp event to irq enable remote 2 aler t event to irq enable remote 1 overtemp event to irq enable remote 1 aler t event to irq enable 05h- 07h reserved 08h tmscfg reserved external vref standby mode 09h tmsbs reserved bank select register bits offset mnemonic 76543210 0ah tchcfst end of conversion open o ts output enable aler t output enable channel overtemp limit exceeded channel temp high limit exceeded channel temp low limit exceeded channel enable 0bh rdcht channel temperature value 0ch chth channel temperature high limit value 0dh chtl channel temperature low limit value 0eh chotl channel overtemperature limit value 0fh reserved
12.0 temperature sensor (tms) (continued) 206 www.national.com 12.5 usage hints 12.5.1 remote diode selection temperature accuracy depends on a good quality transistor, used as a diode-connected small-signal transistor. accuracy has been experimentally verified for the motorola and other devices listed in table 57. a temperature sensor can directly measure the die temperature of cpus with on-board temperature-sensing diodes. the transistor must be a small-signal type with a relatively high forward voltage; otherwise, the a/d input voltage range may be violated. the forward voltage must be greater than 0.25v at 10 m a a t the highest expected temperature. the forward volt- age must be less than 0.95v at 100 m a a t the lowest expected temperature. power transistors do not work. in addition, the base resistance must be less than 100 w . tight specifications for forward-current gain (+50 to +150, for example) indicate devices with consistent vbe characteristics. thermal mass can seriously degrade the temperature sensors effective accuracy. the use of smaller packages for remote sensors, such as sot23s, improves the situation. the delay effect should be expected when measuring temperature using the internal diode. table 57. remote sensor transistor manufacturers 12.5.2 adc noise filtering the adc is an integrating type with inherently good noise rejection, especially of low-frequency signals such as power sup- ply hum. micropower operation places constraints on high-frequency noise rejection; therefore, careful pc board layout and proper external noise filtering are required for high-accuracy remote measurements in electrically noisy environments. high-frequency emi is best filtered at dxp and dxn with an external 2200 pf capacitor. this value can be increased to about 3300pf (max), including cable capacitance. capacitance higher than 3300 pf introduces errors due to the rise time of the switched current source. nearly all noise sources tested cause the adc measurements to be higher than the actual temperature, depending on the frequency and amplitude. 12.5.3 pc board layout 1. place the temperature sensor as close as practical to the remote diode. in a noisy environment, such as a computer motherboard, this distance can be 4 in. to 8 in. (typical) or more as long as the worst noise sources (such as crts, clock generators, memory buses and isa/pci buses) are avoided. 2. do not route the dxp dxn lines next to high-inductance signals. also, do not route the traces across a fast memory bus, which can easily introduce +30?c error, even with good filtering. otherwise, most noise sources are fairly benign. 3. route the dxp and dxn traces in parallel and in close proximity to each other and away from any high-voltage traces such as +12vdc. beware of leakage currents from pc board contamination; e.g., a 20m leakage path from dxp to ground causes about +1?c error. 4. connect guard traces to gnd on either side of the dxp dxn traces (figure 45). with guard traces in place, routing near high-voltage traces is not a problem. 5. route through as few vias and crossunders as possible to minimize copper/solder thermocouple effects. 6. when introducing a thermocouple, make sure that both the dxp and the dxn paths have matching thermocouples. in general, pc board-induced thermocouples are not a serious problem. a copper-solder thermocouple exhibits 3v/?c, and it takes about 200v of voltage error at dxp dxn to cause a +1?c measurement error. so, most parasitic thermocouple errors are swamped out. 7. use wide traces. narrow ones are more inductive and tend to pick up radiated noise. the 10 mil widths and spacings recommended in figure 45 are not absolutely necessary (as they offer only a minor improvement in leakage and noise), but try to use them where practical. manufacturer model central semiconductor (usa) cmpt3904 motorola (usa) mmbt3904 national semiconductor (usa) mmbt3904 rohm semiconductor (japan) sst3904 samsung (korea) kst3904-tf siemens (germany) smbt3904 zetex (england) fmmt3904ct-nd
12.0 temperature sensor (tms) (continued) 207 www.national.com ? keep in mind that copper cannot be used as an emi shield, and only ferrous materials such as steel work well. placing a copper ground plane between the dxp-dxn traces and traces carrying high-frequency noise signals does not help reduce emi. figure 45. dxp/dxn pc traces figure 46. typical operating circuit dxp gnd gnd dxn 10 mil minimum 10 mil 10 mil 10 mil 2n3904 2200 pf dxp dxn
12.0 temperature sensor (tms) (continued) 208 www.national.com 12.5.4 twisted pair and shielded cables for remote sensor distances longer than 8 in. or in particularly noisy environments, a twisted pair is recommended. its prac- tical length is 6 feet to 12 feet (typical) before noise becomes a problem, as tested in a noisy electronics laboratory. for longer distances, the best solution is a shielded twisted pair like that used for audio microphones. connect the twisted pair to dxp and dxn and the shield to gnd and leave the shields remote end unterminated. excess capacitance at dx_ limits practical remote sensor distances. for very long cable runs, the cables parasitic capaci- tance often provides noise filtering, so the 2200 pf capacitor can often be removed or reduced in value. cable resistance also affects remote sensor accuracy: 1 w series resistance introduces about +1/2?c error. 12.5.5 obtaining the specified vlm/tms accuracy to obtain the specified vlm/tms accuracy, use the following sequence on v sb power-up: 1. set the tms logical device base address. 2. enable the tms logical device. 3. write 00h to index 08h of the tms logical device. 4. write 0fh to index 09h of the tms logical device. 5. write 08h to index 0ah of the tms logical device. 6. write 04h to index 0bh of the tms logical device. 7. write 35h to index 0ch of the tms logical device. 8. write 05h to index 0dh of the tms logical device. 9. write 05h to index 0eh of the tms logical device.
209 www.national.com 13.0 legacy functional blocks this chapter briefly describes the following blocks that provide legacy device functions: l keyboard and mouse controller (kbc). l floppy disk controller (fdc). l parallel port. l serial port 1 (sp1), uart functionality for both serial port 1 and serial port 2. l serial port 2 (sp2), infrared functionality. the description of each legacy block includes the sections listed below. for more information about legacy blocks, contact your national representative. l general description. l register map table(s). l bitmap table(s). the register maps in this chapter use the following abbreviations for type: l r/w = read/write. l r = read from a speci?c address returns the value of a speci?c register. w rite to the same address is to a different register. l w = w rite. l ro = read only. l r/w1c = read/write 1 t o clear. w riting 1 t o a bit clears it to 0. writing 0 has no effect. 13.1 keyboard and mouse controller (kbc) 13.1.1 general description the kbc is implemented physically as a single hardware module and houses two separate logical devices: a mouse con- troller and a keyboard controller. the kbc is functionally equivalent to the industry standard 8042a keyboard controller, which may serve as a detailed tech- nical reference for the kbc. 13.1.2 kbc register map 13.1.3 kbc bitmap summary offset mnemonic register name type 00h dbbout read kbc data r dbbin write kbc data w 04h status read status r dbbin write kbc command w register bits offset mnemonic 76543210 00h dbbout kbc data bits (for read cycles) dbbin kbc data bits (for write cycles) 04h status general purpose flags f1 f0 ibf obf dbbin kbc command bits (for write cycles)
13.0 legacy functional blocks (continued) 210 www.national.com 13.2 floppy disk controller (fdc) 13.2.1 general description the generic fdc is a standard fdc with a digital data separator and is dp8473 and n82077 software compatible. the fdc is implemented in this device as follows: l fm and mfm modes are supported. to select either mode, set bit 6 o f the ?rst command byte when writing to/read- ing from a diskette, where: 0 = f m mode 1 = mfm mode l automatic media sense is not supported (msen0-1 pins are not implemented). l drate1 is not supported. l a logic 1 i s returned for all ?oating (tri-state) fdc register bits upon lpc i/o read cycles. 13.2.2 fdc register map offset mnemonic register name type 00h sra status a ro 01h srb status b ro 02h dor digital output r/w 03h tdr tape drive r/w 04h msr main status r dsr data rate select w 05h fifo data (fifo) r/w 06h reserved 07h dir digital input r ccr con?guration control w
13.0 legacy functional blocks (continued) 211 www.national.com 13.2.3 fdc bitmap summary the fdc supports two system operation modes: pc-at mode and ps/2 mode (microchannel systems). unless specifically indicated otherwise, all fields in all registers are valid in both drive modes. register bits offset mnemonic 76543210 00h sra 1 1. applicable only in ps/2 mode. irq pending reserved step trk0 head se- lect index wp head direction 01h srb 1 reserved drive select 0 status wd a t a rd a t a wga te mtr1 mtr0 02h dor motor enable 3 motor enable 2 motor enable 1 motor enable 0 dmaen reset controller drive select 03h tdr reserved tape drive select 1,0 tdr 2 2. applicable only in enhanced tdr mode. reserved d rive id information logical drive exchange tape drive select 1,0 04h msr rqm data i/o direction non-dma execution command in progress drive 3 busy drive 2 busy drive 1 busy drive 0 busy dsr software reset low power reserved precompensation delay select data transfer rate select 05h fifo data bits 07h dir 3 3. applicable only in pc-at compatible mode. dskchg reserved dir 1 dskchg reserved drate 1,0 status high density 07h ccr reserved drate1,0
13.0 legacy functional blocks (continued) 212 www.national.com 13.3 parallel port 13.3.1 general description the parallel port supports all ieee1284 standard communication modes: compatibility (known also as standard or spp), bidirectional (known also as ps/2), fifo, epp (known also as mode 4) and ecp (with an optional extended ecp mode). 13.3.2 parallel port register map the parallel port functional block register maps are grouped according to first and second level offsets. epp and second level offset registers are available only when base address is 8-byte aligned. table 58. parallel port register map for first level offset first level offset mnemonic register name modes (ecr bits) 765 type 000h datar p p data 000 001 r/w 000h afifo ecp address fifo 0 1 1 w 001h dsr status all modes ro 002h dcr control all modes r/w 003h addr epp address 1 0 0 r/w 004h data0 epp data port 0 1 0 0 r/w 005h data1 epp data port 1 1 0 0 r/w 006h data2 epp data port 2 1 0 0 r/w 007h data3 epp data port 3 1 0 0 r/w 400h cfifo pp data fifo 0 1 0 w 400h dfifo ecp data fifo 0 1 1 r/w 400h tfifo test fifo 1 1 0 r/w 400h cnfga con?guration a 1 1 1 ro 401h cnfgb con?guration b 1 1 1 ro 402h ecr extended control all modes r/w 403h eir extended index all modes r/w 404h edr extended data all modes r/w 405h ear extended auxiliary status all modes r/w table 59. parallel port register map for second level offset second level offset register name type 00h control0 r/w 02h control2 r/w 04h control4 r/w 05h pp confg0 r/w
13.0 legacy functional blocks (continued) 213 www.national.com 13.3.3 parallel port bitmap summary the parallel port functional block bitmaps are grouped according to first and second level offsets. table 60. parallel port bitmap summary for first level offset register bits offset mnemonic 76543210 000h datar data bits afifo address bits 001h dsr printer status a ck status pe status slct status err status reserved epp time- out status 002h dcr reserved direction control interrupt enable pp input control printer initialization control automatic line feed control data strobe control 003h addr epp device or register selection address bits 004h data0 epp device or r/w data 005h data1 epp device or r/w data 006h data2 epp device or r/w data 007h data3 epp device or r/w data 400h cfifo data bits 400h dfifo data bits 400h tfifo data bits 400h cnfga reserved bit7ofpp confg0 reserved 401h cnfgb reserved interrupt request value interrupt select reserved dma channel select 402h ecr ecp mode control ecp interrupt mask ecp dma enable ecp interrupt service fifo full fifo empty 403h eir reserved second level offset 404h edr data bits 405h ear fifo tag reserved
13.0 legacy functional blocks (continued) 214 www.national.com table 61. parallel port bitmap summary for second level offset register bits second level offset mnemonic 76543210 00h control0 reserved dcr register live freeze bit reserved epp time- out interrupt mask 02h control2 spp com- patibility channel address enable reserved revision 1.7 or 1.9 select reserved 04h control4 reserved pp dma request inactive time reserved pp dma request active time 05h pp confg0 bit 3 o f cnfga demand dma enable ecp irq channel number pe internal pull-up or pull-down ecp dma channel number
13.0 legacy functional blocks (continued) 215 www.national.com 13.4 uart functionality (sp1 and sp2) 13.4.1 general description both sp1 and sp2 provide uart functionality. the generic sp1 and sp2 support serial data communication with remote peripheral device or modem using a wired interface. the functional blocks can function as a standard 16450 or 16550 or as an extended uart. 13.4.2 uart mode register bank overview four register banks, each containing eight registers, control uart operation. all registers use the same 8-byte address space to indicate offsets 00h through 07h. the bsr register selects the active bank and is common to all banks. see figure 47. figure 47. uart mode register bank architecture bank 0 bank 1 bank 2 bank 3 offset 07h offset 06h offset 05h offset 04h lcr/bsr offset 02h offset 01h offset 00h common register throughout all banks 16550 banks
13.0 legacy functional blocks (continued) 216 www.national.com 13.4.3 sp1 and sp2 register maps for uart functionality table 62. bank 0 register map offset mnemonic register name type 00h rxd receiver data port ro 00h txd transmitter data port w 01h ier interrupt enable r/w 02h eir event identi?cation (read cycles) ro fcr fifo control (write cycles) w 03h lcr 1 1. when bit 7 o f this register is set to 1, bits 6-0 of bsr select the bank, as shown in table 63. line control r/w bsr 1 bank select 04h mcr modem/mode control r/w 05h lsr link status ro 06h msr modem status ro 07h spr/ascr scratchpad/auxiliary status and control r/w table 63. bank selection encoding bsr bits bank selected functionality 76543210 0xxxxxxx 0 uart + ir (sp1 + sp2) 10xxxxxx 1 11xxxx1x 1 11xxxxx1 1 11100000 2 11100100 3 11101000 4 ir only (sp2) 11101100 5 11110000 6 11110100 7 table 64. bank 1 register map offset mnemonic register name type 00h lbgd(l) legacy baud generator divisor port (low byte) r/w 01h lbgd(h) legacy baud generator divisor port (high byte) r/w 02h reserved 03h lcr/bsr line control/bank select r/w 04h - 07h reserved
13.0 legacy functional blocks (continued) 217 www.national.com table 65. bank 2 register map offset mnemonic register name type 00h bgd(l) baud generator divisor port (low byte) r/w 01h bgd(h) baud generator divisor port (high byte) r/w 02h excr1 extended control1 r/w 03h lcr/bsr line control/bank select r/w 04h excr2 extended control 2 r/w 05h reserved 06h txflv tx_fifo level r/w 07h rxflv rx_fifo level r/w table 66. bank 3 register map offset mnemonic register name type 00h mrid module revision id ro 01h sh_lcr shadow o f lcr (read only) ro 02h sh_fcr shadow o f fifo control (read only) ro 03h lcr/bsr line control/bank select r/w 04h-07h reserved
13.0 legacy functional blocks (continued) 218 www.national.com 13.4.4 sp1 and sp2 bitmap summary for uart functionality table 67. bank 0 bitmap register bits offset mnemonic 76543210 00h rxd receiver data bits txd transmitter data bits 01h ier 1 1. non-extended mode. reserved ms_ie ls_ie txldl_ie rxhdl_ie ier 2 2. extended mode. reserved txemp_ie reserved 3 / dma_ie 4 3. in sp1 only. 4. in sp2 only. ms_ie ls_ie txldl_ie rxhdl_ie 02h eir 1 fen1 fen0 reserved rxft ipr1 ipr0 ipf eir 2 reserved txemp_ev reserved 3 / dma_ev 4 ms_ev ls_ev or txhlt_ev txldl_ev rxhdl_ev fcr rxfth1 rxfth0 txfth1 txfth0 reserved txsr rxsr fifo_en 03h lcr 5 5. when bit 7 of this register is set to 1, bits 6-0 of bsr select the bank, as shown in table 63. bkse sbrk stkp eps pen stb wls1 wls0 bsr 5 bkse bank select 04h mcr 1 reserved loop isen or dcdlp rilp rts dtr mcr 2 reserved tx_dfr reserved rts dtr 05h lsr er_inf txemp txrdy brk fe pe oe rxda 06h msr dcd ri dsr cts ddcd teri ddsr dcts 07h spr 1 scratch data ascr 2 reserved txur 4 rxact 4 rxwdg 4 reserved s_oet 4 reserved rxf_tout
13.0 legacy functional blocks (continued) 219 www.national.com table 68. bank 1 bitmap register bits offset mnemonic 76543210 00h lbgd(l) legacy baud generator divisor (least signi?cant bits) 01h lbgd(h) legacy baud generator divisor (most signi?cant bits) 02h reserved 03h lcr/bsr same as bank 0 04h- 07h reserved table 69. bank 2 bitmap register bits offset mnemonic 76543210 00h bgd(l) baud generator divisor low (least signi?cant bits) 01h bgd(h) baud generator divisor high (most signi?cant bits) 02h excr1 btest reserved etdlbk loop reserved ext_sl 03h lcr/bsr same as bank 0 04h excr2 lock reserved presl1 presl0 reserved 05h reserved 06h txflv reserved tfl4 tfl3 tfl2 tfl1 tfl0 07h rxflv reserved rfl4 rfl3 rfl2 rfl1 rfl0 table 70. bank 3 bitmap register bits offset mnemonic 76543210 00h mrid module id (mid 7-4) revision id(rid 3-0) 01h sh_lcr bkse sbrk stkp eps pen stb wls1 wls0 02h sh_fcr rxfth1 rxfth0 txfht1 txfth0 reserved txsr rxsr fifo_en 03h lcr/bsr same as bank 0 04h- 07h reserved
13.0 legacy functional blocks (continued) 220 www.national.com 13.5 ir functionality (sp2) 13.5.1 general description this section describes the ir support registers of serial port 2 (sp2). the uart support registers for both sp1 and sp2 are described in section 13.4. the ir functional block provides advanced, versatile serial communications features with ir capabilities. sp2 supports also two dma channels; the functional block can use either one or both of them. one channel is required for ir-based applications because ir communication works in half duplex fashion. two channels would normally be needed to handle high-speed full-duplex uart based applications. 13.5.2 ir mode register bank overview eight register banks, each containing eight registers, control sp2 operation. banks 0-3 are used to control both uart and ir modes of operation; banks 4-7 are used to control and configure the ir modes of operation only. all registers use the same 8-byte address space to indicate offsets 00h through 07h. the bsr register selects the active bank and is common to all banks. see figure 48. figure 48. sp2 register bank architecture bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 offset 07h offset 06h offset 05h offset 04h lcr/bsr offset 02h offset 01h offset 00h common register throughout all banks ir special banks (banks 4-7)
13.0 legacy functional blocks (continued) 221 www.national.com 13.5.3 sp2 register map for ir functionality . table 71. bank 4 register map offset mnemonic register name type 00h-01h reserved 02h ircr1 ir control 1 r/w 03h lcr/bsr line control/bank select r/w 04h - 07h reserved table 72. bank 5 register map offset mnemonic register name type 00h-02h reserved 03h lcr/bsr line control/bank select r/w 04h ircr2 ir control 2 r/w 05h - 07h reserved table 73. bank 6 register map offset mnemonic register name type 00h ircr3 ir control 3 r/w 01h reserved 02h sir_pw sir pulse width control ( 115 kbps) r/w 03h lcr/bsr line control/bank select r/w 04h-07h reserved table 74. bank 7 register map offset mnemonic register name type 00h irrxdc ir receiver demodulator control ro 01h irtxmc ir transmitter modulator control ro 02h rccfg ceir con?guration ro 03h lcr/bsr line control/bank select r/w 04h ircfg1 ir interface con?guration 1 r/w 05h reserved 06h ircfg3 ir interface con?guration 3 r/w 07h ircfg4 ir interface con?guration 4 r/w
13.0 legacy functional blocks (continued) 222 www.national.com 13.5.4 sp2 bitmap summary for ir functionality table 75. bank 4 bitmap register bits offset mnemonic 76543210 00h- 01h reserved 02h eir reserved ir_sl1 ir_sl0 reserved 03h lcr/bsr same as bank 0 04h- 07h reserved table 76. bank 5 bitmap register bits offset mnemonic 76543210 00h- 02h reserved 03h lcr/bsr same as bank 0 04h ircr2 reserved aux_irrx reserved irmssl ir_fdplx 05h- 07h reserved table 77. bank 6 bitmap register bits offset mnemonic 76543210 00h ircr3 shdm_ds shmd_ds reserved 01h reserved 02h sir_pw reserved spw (3-0) 03h lcr/bsr same as bank 0 04h- 07h reserved
13.0 legacy functional blocks (continued) 223 www.national.com table 78. bank 7 bitmap register bits offset mnemonic 76543210 00h irrxdc dbw (2-0) dfr (4-0) 01h irtxmc mcpw (2-0) mcfr (4-0) 02h rccfg r_len t_ov rxhsc rcdm_ds reserved txhsc rc_mnd1 rc_mmd0 03h lcr/bsr same as bank 0 04h ircfg1 strv_ms sirc (2-0) irid3 iric (2-0) 05h reserved 06h ircfg3 reserved rch (2-0) reserved rclc (2-0) 07h ircfg4 amcfg reserved irsl0_ds rxinv irsl 21_ds reserved
224 www.national.com 14.0 device characteristics 14.1 general dc electrical characteristics 14.1.1 recommended operating conditions 14.1.2 absolute maximum ratings absolute maximum ratings are values beyond which damage to the device may occur. unless otherwise specified, all volt- ages are relative to ground. 14.1.3 capacitance t a = 25 c, f = 1 mhz symbol parameter min typ max unit av dd analog supply voltage (only one) 3.0 3.3 3.6 v v dd supply voltage 3.0 3.3 3.6 v v sb standby voltage 3.0 3.3 3.6 v v bat battery backup supply voltage 2.4 3.0 3.6 v t a operating temperature 0 +70 c symbol parameter conditions min max unit av dd analog supply voltage -0.5 tbd v dd supply voltage - 0.5 +6.5 v v i input voltage - 0.5 v dd + 0.5 v v o output voltage - 0.5 v dd + 0.5 v t stg storage temperature - 65 +165 c p d power dissipation 1w t l lead temperature soldering (10 s) +260 c esd tolerance c zap = 100 pf r zap = 1.5 k w 1 1. value based on test complying with rai-5-048-ra human body model esd testing. 2000 v symbol parameter min typ max unit c in input pin capacitance 57pf c in1 clock input capacitance 5 8 12 pf c io i/o pin capacitance 10 12 pf c o output pin capacitance 68pf
14.0 device characteristics (continued) 225 www.national.com 14.1.4 power consumption under recommended operating conditions 14.2 dc characteristics of pins, by i/o buffer types the following tables summarize the dc characteristics of all device pins described in the signal/pin connection and de- scription chapter. the characteristics describe the general i/o buffer types defined in table 1. for exceptions, refer to sec- tion 14.2.15 on page 228. the dc characteristics of the system interface meet the pci2.1 3.3v dc signaling. 14.2.1 input, cmos compatible symbol: in c 14.2.2 input, pci 3.3v symbol: in pci 14.2.3 input, smbus compatible symbol: in sm symbol parameter conditions typ max unit i cc v dd average main supply current v il = 0.5v, v ih = 2.4v no load 32 50 ma i cclp v dd quiescent main supply current in low power mode v il =v ss ,v ih =v dd no load 1.3 1.7 ma i asb av dd average main supply current tbd tbd ma i sb v sb average main supply current v il = 0.5v, v ih = 2.4v no load 15 ma i sblp v sb quiescent main supply current in low power mode v il =v ss ,v ih =v sb no load 3ma i bat v bat battery supply current v dd ,v sb =0v, v bat =3v 250 na symbol parameter conditions min max unit v ih input high voltage 0.7 v dd 5.5 1 1. not tested. guaranteed by design. v v il input low voltage - 0.5 1 0.3 v dd v i il input leakage current v in =v dd 50 na v in =v ss - 50 na symbol parameter conditions min max unit v ih input high voltage 0.5v dd v dd + 0.5 v v il input low voltage - 0.5 0.3 v dd v l il 1 1. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state out- puts. input leakage current 0 14.0 device characteristics (continued) 226 www.national.com 14.2.4 input, strap pin symbol: in strp 14.2.5 input, ttl compatible symbol: in t 14.2.6 input, ttl compatible with schmitt trigger symbol: in ts v il input low voltage - 0.5 1 0.8 v i il input leakage current v in =v dd 10 m a v in =v ss - 10 m a 1. not tested. guaranteed by design. symbol parameter conditions min max unit v ih input high voltage 0.6 v dd 1 5.5 1 1. not tested. guaranteed by design. v i il input leakage current during reset: v in =v dd 150 m a v in =v ss - 10 m a symbol parameter conditions min max unit v ih input high voltage 2.0 5.5 1 1. not tested. guaranteed by design. v v il input low voltage - 0.5 1 0.8 v i il input leakage current v in =v dd 10 m a v in =v ss - 10 m a symbol parameter conditions min max unit v ih input high voltage 2.0 5.5 1 1. not tested. guaranteed by design. v v il input low voltage - 0.5 1 0.8 v i il input leakage current v in =v dd 10 m a v in =v ss - 10 m a v h input hysteresis 250 mv symbol parameter conditions min max unit
14.0 device characteristics (continued) 227 www.national.com 14.2.7 output, pci 3.3v symbol: o pci 14.2.8 output, totem-pole buffer symbol: o p/n output, totem-pole buffer that is capable of sourcing p ma and sinking n ma 14.2.9 output, open-drain buffer symbol: od n output, open-drain output buffer, capable of sinking n ma. output from these signals is open-drain and cannot be forced high. 14.2.10 input, analog symbol: in an1 input, analog to vlm. 14.2.11 input, analog symbol: in an2 input, analog to reference voltage. symbol parameter conditions min max unit v oh output high voltage l out = -500 m a 0.9 v dd v v ol output low voltage l out =1500 m a 0.1 v dd v symbol parameter conditions min max unit v oh output high voltage i oh = - p ma 2.4 v v ol output low voltage i ol = n ma 0.4 v symbol parameter conditions min max unit v ol output low voltage i ol = n ma 0.4 v symbol parameter conditions 1 1. all parameters speci?ed for 0 c t a 70 c. av cc = 3.3v 10%, unless otherwise speci?ed and v ref = 1.235 or av dd. min typ max unit i al analog input leakage current 1 m a r ain analog input resistance 2 2. the resistance between the device input and the internal analog input capacitance. 250 w c ain analog input capacitance 15 pf symbol parameter conditions 1 1. all parameters speci?ed for 0 c t a 70 c. av cc = 3.3v 10%, unless otherwise speci?ed and v ref = 1.235 or av dd . min typ max unit v refe external reference voltage tbd 1.235 tbd v r vrefe v ref input dc resistance 2 2. valid only for external v ref ; value changes during the conversion. 536k w
14.0 device characteristics (continued) 228 www.national.com 14.2.12 input, analog symbol: in an3 input, analog to tms. 14.2.13 output, analog symbol: o an1 output, analog to reference voltage. 14.2.14 output, analog symbol: o an2 output, analog to tms. 14.2.15 exceptions 1. all pins are back-drive protected, except for the output pins with pci buffer type. 2. the following pins have a static pull-up resistor and therefore may have input leakage current (when v in =v ss ) o f about (-)160 m a: a ck, afd_ dstrb, err, gpio40-47, gpio30-34, gpio20-27, gpio16-17, gpio10-14. gpio00-07, init, p12, p16, p17, pe, slin_ astrb, stb_ write. 3. the following pins have a static pull-down resistor and therefore may have input leakage current (when v in =v dd )of about 130 m a: busy_ w ait, pe, slct. 4. output from slct, busy_ wait (and pe if bit 2 o f p p confg0 register is 0) is open-drain in all spp modes, except in spp-compatible mode when the setup mode is ecp-based fifo and bit 4 o f the control2 parallel port register is 1. otherwise, output from these signals is level 2. external 4.7 kw pull-up resistors should be used. 5. output from ack, err (and pe if bit 2 o f p p confg0 register is set to 1) is open-drain in all spp modes, except in spp- compatible mode when the setup mode is ecp-based fifo and bit 4 o f the control2 parallel port register is set to 1. otherwise, output from these signals is level 2. external 4.7 kw pull-up resistors should be used. 6. output from stb, afd, init, slin is open-drain in all spp modes, except in spp-compatible mode when the setup mode is ecp-based (fifo). otherwise, output from these signals is level 2. external 4.7 k w pull-up resistors should be used. 7. output from pd7-0 is open-drain in all spp modes, except in spp-compatible mode when the setup mode is ecp-based (fifo) and bit 4 o f the control2 parallel port register is 1. otherwise, output from these signals is level 2. external 4.7 k w pull-up resistors should be used. 8. i oh is valid for a gpio pin only when it is not configured as open-drain. 9. p12, p16 and p17 are driven high for about 100 ns after a low-to-high transition, during which it is capable of sourcing 2 ma. symbol parameter conditions min typ max unit v dn d- source voltage 0.7 v symbol parameter conditions min typ max unit v refe external reference voltage 1.233 1.235 1.237 v r vrefe v ref input dc resistance 1 1. valid only for external v ref ; value changes during the conversion. 536k w symbol parameter conditions min typ max unit i dph diode source current d+ = d - + 0.65v; high level 80 120 m a i dpl low l evel 8 1 2 m a
14.0 device characteristics (continued) 229 www.national.com 14.3 internal resistors 14.3.1 pull-up resistor symbol: pu nn . 14.3.2 pull-down resistor symbol: pd nn . 14.4 analog characteristics 14.4.1 vlm symbol parameter conditions typical min max unit r pu pull-up equivalent resistance v dd = 3.3v nn nn - 30% nn +30% k w symbol parameter conditions typical min max unit r pd pull-down equivalent resistance v dd = 3.3v nn nn - 30% nn +30% k w symbol parameter conditions 1 1. all parameters speci?ed for 0 c t a 70 c and av cc = 3.3v 5% unless otherwise speci?ed and external v ref = 1.211v. min typical max unit v res resolution 8 bit v dnl differential (non-linearity) error 2 2. the maximum difference between an ideal step size of 1 lsb and any actual step size. 0.5 3 3. no missing codes. lsb v ref reference voltage input 4 4. the voltage connected to this input serves a s the reference voltage used to calculate the actual input voltatge. 1.211 v acu accuracy 5 5. total unadjusted error (incoludes the offset, gain, integral n0on-linearity and quantization (0.5 lsb) errors). 0v v in 0.95 v fs 6 lsb v fs full scale voltage 2.967 v v in input voltage range 0 2.45*v ref v t act vlm activation time 6 6. time from when the vlmcfg register standby mode enable bit = 0 until valid conversions are possible. 100 m s
14.0 device characteristics (continued) 230 www.national.com 14.4.2 tms symbol parameter conditions 1 1. all parameters speci?ed for 0 c t a 70 c. av cc = 3.3v 10% unless otherwise speci?ed and external v ref = 1.211v. min typ max unit t rac1 accuracy using remote diode t a = -40 c t o +125 c-9 +9c t rac2 t a = +40 c t o +100 c-5 +5c t lac1 accuracy using local diode 2 2. not tested; guaranteed by design. t a = -40 c t o +125 c-5 +5c t lac2 t a = +40 c t o +100 c-2 +2c t resb resolution 8 bits t resc 1 c v ref reference voltage input 3 3. when using input with value other than speci?ed, temperature reading accuracy is affected. 1.211 v t conv temperature conversion time (per channel) 100 ms
14.0 device characteristics (continued) 231 www.national.com 14.5 ac electrical characteristics 14.5.1 ac test conditions figure 49. ac test conditions, t a =0 cto70 c, v dd = 5.0v 10% notes: 1. c l = 100 pf for all output pins except o pci , and c l = 50pf for outputs of type o pci . these values include both jig and scope capacitance. 2. s 1 = open for push-pull output pins. s 1 = v dd for high impedance to active low and active low to high-impedance measurements. s 1 = gnd for high impedance to active high and active high to high-impedance measurements. r l = 1.0k w for m p interface pins. 3. for the fdc open-drive interface pins, s 1 = v dd and r l = 150 w . 14.5.2 clock timing . symbol parameter 48 mhz min max unit t ch clock high pulse width 1 1. not tested. guaranteed by design. 8.4 ns t cl clock l ow pulse width 1 8.4 ns t cp clock period 1 20 21.5 ns device under test 0.1 m f input output r l c l s 1 load circuit (notes 1, 2, 3) ac testing input, output waveform v dd 2.4 0.4 2.0 0.8 test points 2.0 0.8 clkin t cl t cp t ch
14.0 device characteristics (continued) 232 www.national.com 14.5.3 lclk and lreset symbol parameter min max units t cyc 1 1. the pci may h ave a ny clock frequency between nominal dc and 33 mhz. device operational parameters at frequencies under 16 mhz may be guaranteed by design rather than by testing. the clock frequency may b e changed at any time during the operation of the system as long as the clock edges remain clean (monotonic) and the minimum cycle and high and low times are not violated. the clock m ay only be stopped in a low state. lclk cycle time 30 ns t high lclk high time 11 ns t low lclk low time 11 ns - lclk slew rate 2 2. rise and fall times are speci?ed in terms of the edge rate measured in v/ns. this slew rate must be met across the minimum peak-to-peak por- tion of the clock wavering as shown below. 1 4 v/ns - lreset slew rate 3 3. the minimum lreset slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise cannot make a n otherwise monotonic signal appear to bounce in the switching range. 50 mv/ns 0.6 v dd 0.2 v dd 0.5 v dd 0.4 v dd 0.3 v dd 0.4 v dd p-to-p (minimum) t high t low 3.3v clock t cyc
14.0 device characteristics (continued) 233 www.national.com 14.5.4 lpc and serirq signals symbol figure description reference conditions min max unit t val output output valid delay after re clk 11 ns t on output float to active delay after re clk 2 ns t off output active t o float delay after re clk 28 ns t su input input setup time before re clk 7 ns t hi input input hold time after re clk 0 ns lclk lpc signals/ serirq t on output t val t off lclk lpc signals/ serirq t su t hi input valid input
14.0 device characteristics (continued) 234 www.national.com 14.5.5 serial port, sharp-ir, sir and consumer remote control timing symbol parameter conditions min max unit t bt single bit time in serial port and sharp-ir transmitter t btn - 25 1 1. t btn is the nominal bit time in serial port, sharp-ir, sir and consumer remote control modes. i t i s deter- mined by the setting of the baud generator divisor registers. t btn +25 ns receiver t btn - 2% t btn +2% ns t cmw modulation signal pulse width in sharp-ir and consumer remote control transmitter t cwn - 25 2 2. t cwn is the nominal pulse width of the modulation signal for sharp-ir and consumer remote control modes. it is determined by the mcpw ?eld (bits 7-5) of the irtxmc register and the txhsc bit (bit 2) of the rccfg register. t cwn +25 ns receiver 500 ns t cmp modulation signal period in sharp-ir and consumer remote control transmitter t cpn - 25 3 3. t cpn is the nominal period of the modulation signal for sharp-ir and consumer remote control modes. i t i s determined by the mcfr ?eld (bits 4-0) of the irtxmc register and the txhsc bit (bit 2) of the rccfg reg- ister. t cpn +25 ns receiver t mmin 4 4. t mmin and t mmax de?ne the time range within which the period of the incoming subcarrier signal has to fall in order for the signal to be accepted by the receiver. these time values are determined by the contents of the irrxdc register and the setting of the rxhsc bit (bit 5) of the rccfg register. t mmax 4 ns t spw sir signal pulse width transmitter, variable ( 3 / 16 )xt btn - 15 1 ( 3 / 16 )xt btn + 15 1 ns transmitter, fixed 1.48 1.78 m s receiver 1 m s s drt sir data rate tolerance. % o f nominal data rate. transmitter 0.87% receiver 2.0% t sjt sir leading edge jitter. % o f nominal bit duration. transmitter 2.5% receiver 6.5% serial port t cmw t cmp sharp-ir consumer remote control t bt sir t spw
14.0 device characteristics (continued) 235 www.national.com 14.5.6 modem control timing 14.5.7 fdc write data timing t drp t icp t wdw values symbol parameter min max unit t l ri2,1 low time 10 ns t h ri2,1 high time 10 ns t sim delay t o set irq from modem input 40 ns symbol parameter min max unit t hdh hdsel hold from wga te inactive 1 1. not tested. guaranteed by design. 100 m s t hds hdsel setup to wga te active 1 100 m s t wdw write data pulse width see t drp ,t icp and t wdw values in table below data rate t drp t icp t icp nominal t wdw t wdw minimum unit 1 mbps 1000 6xt cp 1 1. t cp is the clock period defined in the clock timing section on page 231. 125 2 x t icp 250 ns 500 kbps 2000 6xt cp 1 125 2 x t icp 250 ns 300 kbps 3333 10 x t cp 1 208 2 x t icp 375 ns 250 kbps 4000 12 x t cp 1 250 2 x t icp 500 ns cts, dsr, dcd interrupt (read msr) ri t sim t sim t sim t h t l (read msr) t hds t hdh t wdw hdsel wgate wdata
14.0 device characteristics (continued) 236 www.national.com 14.5.8 fdc drive control timing 14.5.9 fdc read data timing symbol parameter min max unit t dst dir setup to step active 1 1. not tested. guaranteed by design. 6 m s t iw index pulse width 100 ns t std dir hold from step inactive t str ms t stp step active high pulse width 1 8 m s t str step rate time 1 0.5 ms symbol parameter min max unit t rdw read data pulse width 50 ns t iw t stp t dst t str t std dir step index t rdw rdata
14.0 device characteristics (continued) 237 www.national.com 14.5.10 standard parallel port timing typical data exchange 14.5.11 enhanced parallel port timing symbol parameter conditions typ max unit t pdh port data hold these times are system dependent and are therefore not tested. 500 ns t pds port data setup these times are system dependent and are therefore not tested. 500 ns t sw strobe width these times are system dependent and are therefore not tested. 500 ns symbol parameter min max epp 1.7 epp 1.9 unit t ww19a write active from w ait low 45 4 ns t ww19ia write inactive from w ait low 45 4 ns t wst19a dstrb or astrb active from w ait low 65 4 ns t west dstrb or astrb active after write active 10 44 ns t wpdh pd7-0 hold after write inactive 0 44 ns t wpds pd7-0 valid after write active 15 44 ns t epdw pd7-0 valid width 80 44 ns t epdh pd7-0 hold after dstrb or astrb inactive 0 44 ns t pds t pdh t sw busy ack pd7-0 stb write dstrb astrb pd7-0 wait valid t ww19ia t wpdh t epdh t epdw or t ww19a t wst19a t wpds t west t wst19a
14.0 device characteristics (continued) 238 www.national.com 14.5.12 extended capabilities port (ecp) timing forward mode reverse mode symbol parameter min max unit t ecdsf data setup before stb active 0ns t ecdhf data hold after busy inactive 0ns t eclhf busy active after stb active 75 ns t echhf stb inactive after busy active 01s t echlf busy inactive after stb active 035ms t ecllf stb active after busy inactive 0ns symbol parameter min max unit t ecdsr data setup before ack active 0ns t ecdhr data hold after afd active 0ns t eclhr afd inactive after ack active 75 ns t echhr ack inactive after afd inactive 035ms t echlr afd active after ack inactive 01s t ecllr ack active after afd active 0ns pd7-0 stb busy t echhf t echlf t ecllf t ecdsf t eclhf t ecdhf afd pd7-0 ack afd t echhr t echlr t ecllr t ecdsr t eclhr t ecdhr busy
pc87366 128-pin lpc superi/o with system hardware monitoring and midi and game ports physical dimensions all dimensions are in millimeters. plastic quad flatpack (pqfp), jedec order number pc87365-xxx/vla ns package number vla128a life support policy national?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.national.com national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and nati onal reserves the right at any time without notice to change said circuitry and specifications. national semiconductor corporation, americas email: new.feedback@nsc.com national semiconductor europe fax: +49 (0) 1 80 530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 fran?ais tel: +33 (0) 1 41 91 87 90 national semiconductor asia pacific fax: 65-250-4466 email: ap.support@nsc.com tel: 65-254-4466 national semiconductor japan fax: 81-3-5639-7507 email: nsj.crc@jksmtp.nsc.com tel: 81-3-5639-7560

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